http://publicationslist.org/data/vadim.gektin/atom.xml Vadim Gektin, Ph.D., P.E.http://publicationslist.org/vadim.gektin$basepathfavicon.icoRecent additions to Vadim Gektin, Ph.D., P.E.'s PublicationsList.org pagehttp://publicationslist.org/publications.png2020-06-21T05:32:25Z http://publicationslist.org/vadim.gektin/refid59 2019-05-15T23:53:13Z

A fluid coupling mating apparatus and method. Included is at least one mating member for removably coupling with another mating member for allowing fluid to pass therebetween. A lock is movably coupled to the at least one mating member. Still yet, a holder is coupled to the lock for holding the lock in relation to the holder during at least a portion of the removable coupling of the at least one m...<br/><br/>M Bai, V Gektin (2019) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid68 2020-06-21T05:27:02Z

A device includes a charger case. Charging electronics are supported within the case. An electrical connector is coupled to the charging electronics for coupling to a power source. A cooling element is coupled to the charger case and extendable to an extended position from the case such that a cooling surface area of the charger case is increased.<br/><br/>V Gektin, Q Li, G Yang (2019) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid70 2020-06-21T05:31:50Z

Increasing power densities in data centers due to the rise of Artificial Intelligence (AI), high-performance computing (HPC) and machine learning compel engineers to develop new cooling strategies and designs for high-density data centers. Two-phase cooling is one of the promising technologies which exploits the latent heat of the fluid. This technology is much more effective in removing high heat...<br/><br/>S Khalili, S Rangarajan, B Sammakia, V Gektin (2019) <i>ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK 2019) Anaheim, California, USA</i> <br/>

http://publicationslist.org/vadim.gektin/refid69 2020-06-21T05:31:29Z

There are many widely available heat transfer technologies that use forced air and vapor chambers to solve thermal problems up to 40 Watts/cm 2 . The chart in Figure 1 provides an overview of today's cooling technologies, markets, and total device power in Watts while introducing heat flux limits in W/cm 2 for air cooling versus liquid cooling. The present study investigates the characterization o...<br/><br/>G Refai-Ahmed, B Philofsky, V Gektin, B Sammakia, H Do, S Rangarajan (2019) <i>IEEE 21st Electronics Packaging Technology Conference (EPTC)</i> <br/>

http://publicationslist.org/vadim.gektin/refid55 2020-06-21T05:29:19Z

Recent commercial efforts have reestablished the benefits of cooling server modules using direct liquid cooling (DLC) technology. The primary drivers behind this technology are the increase in chip densities and the absolute need to reduce the overall data center power usage. In DLC technology, a cold plate is situated on top of the chip with thermal interface material between the chip and the col...<br/><br/>B Ramakrishnan, S Alkharabsheh, Y Hadad, P R Chiarot, K Ghose, B Sammakia, V Gektin, W Chao (2018) <i>34th SEMI-THERM Symposium, DoubleTree, San Jose, CA, USA, March 19-24, 2018.</i> <br/>

http://publicationslist.org/vadim.gektin/refid56 2020-06-21T05:29:57Z

Today’s compact electronic packages consist of chips with different restrictions on their operating temperatures. To ensure reliability in such devices, each component must be kept within their temperature limits. This often results in overcooling the entire package to meet the lowest temperature limit that exists within the system, leading to an inefficient thermal management scheme. By impleme...<br/><br/>S U Yuruker, R K Mandel, D G Bae, V Gektin, M M Ohadi (2018) <i>17th IEEE ITHERM Conference, Sheraton Hotel & Marina, San Diego, CA, USA, May 29 - June 1, 2018</i> <br/>

http://publicationslist.org/vadim.gektin/refid57 2020-06-21T05:30:39Z

Miniaturization of microelectronic components comes at a price of high heat flux density. By adopting liquid cooling, the rising demand of high heat flux devices can be met while the reliability of the microelectronic devices can also be improved to a greater extent. Liquid cooled cold plates are largely replacing air based heat sinks for electronics in data center applications, thanks to its larg...<br/><br/>B Ramakrishnan, Y Hadad, S Alkharabsheh, P R Chiarot, K Ghose, B Sammakia, V Gektin, W Chao (2018) <i>2018 17th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)</i> <br/>

http://publicationslist.org/vadim.gektin/refid60 2020-06-21T05:30:57Z

In the recent years, lidless (bare) die packaging starts to appear in the high power applications with a large die size, complementing the conventional lidded packaging. Given the vast parameters’ space of the lidded vs. lidless designs, a systematic study is necessary to develop a clear and practical design recommendations. In this work, an analytical study is conducted to assess the sensitivit...<br/><br/> X Huang, V Gektin (2018) <i>ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK 2018), San Francisco, California, USA, 2018</i> <br/>

http://publicationslist.org/vadim.gektin/refid58 2019-05-15T23:50:46Z

The present disclosure relates to a cold plate and vapor chamber for conduction cooling of one or more printed circuit boards in a printed circuit board (PCB) enclosure. The cold plate may include a planar surface at an oblique angle relative to an axis along which the PCB assembly is inserted into the enclosure. The PCB assembly may include a vapor chamber having a complementary obliquely angled ...<br/><br/>M. Bai, V. Gektin (2018) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid67 2019-06-28T00:17:27Z

J. He, G. Wang, V. Gektin (2018) <i>1st High-Power ASICs Engineering Challenges Workshop (by invitation), Scottsdale, Arizona, USA, November 29-30, 2018</i> <br/>

http://publicationslist.org/vadim.gektin/refid52 2019-05-15T23:49:53Z

M. Bai, V. Gektin (2017) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid51 2020-06-21T05:24:23Z

This paper reviews thermal management challenges encountered in a wide range of electronics cooling applications from large-scale (data center and telecommunication) to small-scale systems (personal, portable/wearable, and automotive). This paper identifies drivers for progress and immediate and future challenges based on discussions at the 3rd Workshop on Thermal Management in Telecommunication S...<br/><br/>S V Garimella, T Persoons, J Weibel, and V Gektin (2017) <i>IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY</i> 7: 8 1191-1205<br/>

http://publicationslist.org/vadim.gektin/refid54 2018-01-02T22:29:54Z

Increasing power density of electronic chips keeps pushing the cooling solution to extreme optimization. In recent years, bare die (direct die) starts to appear in high power applications with a large die size, replacing the conventional lidded packaging [1]. However, there is no clear and practical design guidance due to the vast parameter space and a lack of systematic studies. In this work, an ...<br/><br/>X. Huang, J. Behm, V. Gektin (2017) <i>IMAPS Advanced Technology Workshop on Thermal Management, IMAPS ATW 2017, Toll House Hotel, Los Gatos, CA, USA, November 7-9, 2017</i> <br/>

http://publicationslist.org/vadim.gektin/refid53 2018-01-02T22:02:38Z

V. Gektin, X. Fu, C. Yang (2017) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid66 2019-06-03T06:28:18Z

V Gektin, X Huang, L Jin (2017) <i>9th Cooling Technology Workshop (by invitation), Yokohama, Japan, November 1-2, 2017</i> <br/>

http://publicationslist.org/vadim.gektin/refid50 2016-02-04T20:59:49Z

The thermal efficiency of dual-column chassis can be improved by re-locating line card to connection plane (LC-to-CP) interfaces to the center of the connection plane, as this allows inter line card channels (inter-LC channels) to be routed in a manner that avoids bisecting the thermal throughways over which convection cooling air is circulated to the line cards. One technique for centrally locati...<br/><br/>V. Gektin and J. Xu (2016) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid49 2019-05-16T01:49:43Z

Apparatus and method embodiments are provided for a heat sink mounted on a printed circuit board using a back plate with preload. An apparatus comprises a circuit component, a heat sink on a first side of the circuit component a, a back plate having an initial curvature and positioned at a second side of the circuit component opposite to the heat sink, and one or more screws through the back plate...<br/><br/>V. Gektin; Y. Jin (2015) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid65 2019-06-03T06:19:25Z

V Gektin (2014) <i>6th Cooling Technology Workshop (by invitation), Yokohama, Japan, October 23-24, 2014</i> <br/>

http://publicationslist.org/vadim.gektin/refid47 2019-05-16T01:49:04Z

Lower semiconductor dies in 2.5 D semiconductor packaging configurations can be cooled by thermally coupling the lower semiconductor dies to a heat sink positioned above the interposer, to an upper semiconductor die, to a heat sink affixed beneath a substrate, or to free-flowing air circulating above the interposer or beneath the substrate. The thermal coupling can be achieved using heat pipes, th...<br/><br/>A. Mohammed, V. Gektin (2014) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid48 2019-05-16T01:48:24Z

A chassis including a slot configured to receive a printed circuit board having a baffle position pin and electronic components mounted thereon, a guide mechanism mounted within the slot, and a carriage moveably mounted within the slot and biased toward a slot opening by the guide mechanism, the carriage including a baffle suitable to manipulate a flow of air through the slot, the carriage configu...<br/><br/>Y Jin;J Xu; Jiye, V Gektin (2014) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid46 2013-02-21T02:33:57Z

A method for the assembly of a semiconductor package that includes cleaning a surface of a chip and a surface of a heat removal device by reverse sputtering is given. The method includes sequentially coating the surface of the chip and the surface of the heat removal device with an adhesive layer, a barrier layer, and a protective layer over a target joining area. The chip and the heat removal dev...<br/><br/>S Ankireddi, V Gektin, J Jones, M Stern (2013) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid43 2013-02-21T02:36:37Z

A multi-surface compliant heat removal process that includes identifying components to share a heat rejecting device; applying non-adhesive film to the components; identifying a primary component of the components; and applying phase change material on each of the components, other than the primary component. The phase change material is placed on top of the non-adhesive film. The process also inc...<br/><br/>V Gektin, D Malladi (2012) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid64 2020-06-21T05:27:58Z

V Gektin (2012) <i>4th Cooling Technology Workshop (by invitation), Shenzhen, China, November 5, 2012</i> <br/>

http://publicationslist.org/vadim.gektin/refid44 2019-05-16T01:47:25Z

A stacked microprocessor package architecture includes one or more microprocessor packages, the microprocessor packages including one or more microprocessor die disposed on a substrate, a satellite die, a thermal bus thermally coupled to the microprocessor die and thermally connected to system cooling, and a power bus providing power to the microprocessor die and coupled to system power. The micro...<br/><br/>S Ankireddi, V Gektin (2012) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid42 2013-02-21T02:35:07Z

In at least one embodiment, an interposer for a board interconnect system is provided. The interposer comprises a frame and at least one interconnect. The frame receives a substrate. The substrate includes a top side, a bottom side, and a conductive interface. The conductive interface extends through the top side and the bottom side for delivering an electrical signal from an electrical device pos...<br/><br/>V. Gektin, D. Copeland (2012) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid63 2019-06-03T06:05:35Z

V Gektin, J Xu, Y Jin, D Le (2012) <i>3rd Cooling Technology Workshop (by invitation), Santa Clara, CA, USA, April 25-26, 2012</i> <br/>

http://publicationslist.org/vadim.gektin/refid41 2019-05-16T01:46:26Z

A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device, applying non-adhesive film to the one or more components, identifying a primary component of the one or more components, and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of ...<br/><br/>V Gektin, D Malladi (2011) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid22 2019-06-03T05:35:13Z

V. Gektin (2010) <i>12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electric Systems, ITherm 2010, Las Vegas, NV, USA</i><br/>

http://publicationslist.org/vadim.gektin/refid61 2019-06-03T05:35:00Z

S. Prstic, M. Iyengar, M. Arik, V. Gektin, M. Hodes, S. Narasimhan, K. Geisler (2010) <i>12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electric Systems, ITherm 2010, Las Vegas, NV, USA</i><br/>

http://publicationslist.org/vadim.gektin/refid40 2019-05-16T01:45:52Z

A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite interconnect. The die-attach composite interconnect includes a plurality of carbon nanotub...<br/><br/>V. Gektin, D. Copeland (2010) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid6 2010-07-08T22:54:19Z

This paper described a ceramic ball grid array (CBGA) and its second level reliability. The CBGA uses a substrate with high coefficient of thermal expansion (CTE) and leadfree soldering. The reworkability of the BGA package and board was also studied. The results have shown that this package is reworkable without a significant reliability reduction in the board level reliability. The reliability o...<br/><br/>D Xie ; Gektin, V. ; Geiger, D. (2009) <i>59th Electronic Components and Technology Conference, 2009. ECTC 2009</i> 109 - 116<br/>

http://publicationslist.org/vadim.gektin/refid62 2019-06-03T05:42:14Z

As the microelectronics industry continues to trend towards smaller, lighter, and higher power devices, thermal management is becoming more important than ever. Thermal interface materials (TIMs) play a crucial role in removing heat from both bare die and lidded packages. A serious challenge the industry has been facing is the lack of an agreed upon test standard that is specifically tailored for ...<br/><br/>Y Chen, S Pecavar, V Gektin (2009) <i>ASME 2009 InterPACK Conference, San Francisco, California, USA, 2009</i> <br/>

http://publicationslist.org/vadim.gektin/refid34 2019-05-16T01:45:19Z

A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may...<br/><br/>V. Gektin, D. Copeland (2009) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid23 2019-06-07T18:26:36Z

As power levels and heat generation increase in high-performance CPUs and other semiconductor devices, the thermal performance of commonly used packaging components is becoming a limiting factor. Many such devices are mounted in flip chip packages, in which the die is underfilled on the active side and in direct contact with a thermal interface material (TIM), with a metal or ceramic lid attached ...<br/><br/>V. Gektin, M Stern, L. Larson, D. Bhagwagar, J. Marin, and A. Nakayoshi (2008) <i>Advanced Packaging</i> : <br/>

http://publicationslist.org/vadim.gektin/refid24 2019-06-13T18:55:12Z

We have evaluated a new Ag-filled silicone thermal interface material (TIM) for its sensitivity to lid finish and impact on imaging discontinuities in the die/lid (TIM1) layer, in conjunction with two high performance lid materials, as a part of our advanced packaging technology development effort. Thermal and mechanical (shear stress and lid pull) measurements have been carried out on a number of...<br/><br/>M Stern, B Melanson, V Gektin, P Hundt, C Arroyo, V. Gupta, K. Nakayoshi, L Larson, J Marin, D. McDougall, D. Bhagwagar (2007) <i>ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference</i> 309 - 318<br/>

http://publicationslist.org/vadim.gektin/refid33 2019-05-16T01:44:50Z

A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The in...<br/><br/>V. Gektin, D. Malladi (2007) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid32 2019-05-16T01:44:02Z

A field-replaceable active pumped liquid heat sink module includes a liquid pump, a radiator, an optional receiver, and a gasketed cold heat exchanger box, all of which are connected together in a liquid pump loop through which a coolant such as water is circulated. The liquid pump, radiator, optional receiver and gasketed cold heat exchanger box are in a liquid pump loop and are self-contained in...<br/><br/>A. Heydari and V. Gektin (2007) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid31 2019-05-16T01:43:15Z

A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wa...<br/><br/>B. Sen, S. Kirkman, and V. Gektin (2006) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid2 2010-07-08T23:09:15Z

A test apparatus and methodology have been developed to provide accurate measurement of the thermal resistance of interface materials for predictive modeling simulations and selection of optimal cooling solution for high-power electronic modules. A guarded heat flow apparatus, based on the ASTM D5470 standard, using calibrated RTDs embedded in precision-machined meter blocks, has been developed to...<br/><br/>M Stern; D. Kearns.; V. Gektin.; G. Jhoty (2006) <i>The Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06.</i> 505 - 511<br/>

http://publicationslist.org/vadim.gektin/refid14 2019-06-13T22:00:40Z

The paper parametrically assesses the impact of the voids/delamination on the system thermal performance. Analysis is carried out numerically and validated against experimental data (thermal measurements and C-SAM images). Topics covered include the relationship between voids/delamination and TIMs’ and heat spreader’s effective thermal conductivity; sensitivity of the system thermal performanc...<br/><br/>V. Gektin (2005) <i>The Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference INTERpack '05. San Francisco, CA, USA</i> CD-ROM [Cited by 3]<br/>

http://publicationslist.org/vadim.gektin/refid12 2019-06-13T22:07:55Z

Paper defines test requirement guidelines for determining reliability and functionality of TIM2 materials to be used in Sun products. Test requirements are defined as guidelines, rather than strict specifications, due to the unique nature presented by various TIM materials and actual products. These guidelines are used by engineers engaged in cooling solution development, and are also beneficial t...<br/><br/>S. Pecavar, M. Stern, D. Kearns, V. Gektin, T. Chen, and B. Ong (2005) <i> IMAPS Advanced Technology Workshop on Thermal Management, IMAPS ATW 2005, Dinah's Garden Hotel, Palo Alto, California USA October 23– 26, 2005 </i> CD-ROM<br/>

http://publicationslist.org/vadim.gektin/refid3 2019-06-13T22:11:11Z

High performance thermal greases have been evaluated in three separate environments: ideal laboratory, in situ laboratory, and system mockup testing to better understand how bulk and interfacial thermal properties, in combination with the test vehicles used, effect the resultant thermal performance. The three methodologies are described and measurements on a baseline material reported.<br/><br/>M. Stern. ; V. Gektin. ; S. Pecavar. ; D. Kearns ; T. Chen (2005) <i>Twenty First Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 2005 IEEE</i> 39 - 43 [Cited by 3]<br/>

http://publicationslist.org/vadim.gektin/refid13 2019-06-13T22:06:55Z

Novel packaging materials with the promise of high thermal conductivity (TC) and low or tailored coefficients of thermal expansion (CTE) are increasingly available as heat spreaders and thermal interface materials (TIMs). We have evaluated a number of these materials including 2 diamond composites, Cu-ceramic functionally graded materials, baseline metal filled epoxies and 2 metallic or solder-bas...<br/><br/>M. Stern, D. Kearns, R. Melanson, G. Jhoty, V. Gektin, and S. Pecavar (2005) <i> IMAPS Advanced Technology Workshop on Thermal Management, IMAPS ATW 2005, Dinah's Garden Hotel, Palo Alto, California USA October 23– 26, 2005 </i> CD-ROM<br/>

http://publicationslist.org/vadim.gektin/refid15 2019-06-13T21:58:56Z

Advances in processor design have been made possible in part by increases in the packaging density of electronics. At the same time, combination of increased power dissipation and packaging density has led to substantial growth in the chip and system heat fluxes and amplified complexity in electrical signal integrity and mechanical stack-up design in the recent years, particularly, in the high-end...<br/><br/>A. Heydari and V. Gektin (2005) <i>The Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference INTERpack '05. San Francisco, CA, USA</i> CD-ROM<br/>

http://publicationslist.org/vadim.gektin/refid30 2019-05-16T01:42:40Z

A device for the transfer of heat away from a heat source comprising a base having first and second surfaces a plurality of fins extending adjacent to the second surface of the base. The base further including a chamber disposed between the first surface and the second surface of the base. The chamber further including a divider disposed therein adjacent the first surface. A pump is also disposed ...<br/><br/>V. Gektin, S. Novotny, and M. Vogel (2005) <i>The United States Patent and Trademark Office (USPTO) [Cited by 1]</i><br/>

http://publicationslist.org/vadim.gektin/refid9 2019-06-14T23:34:21Z

Many advances in Complementary Metal Oxide Semiconductor (CMOS) technology (deep sub micron feature scales, GHz frequencies, and Silicon On Insulator (SOI)fabrication) have been made possible by increases in the packaging density of electronics. These advances began with the introduction of very large scale integration (VLSI). The combination of increased power dissipation and packaging density le...<br/><br/>Heydari, A. ; Gektin, V. (2004) <i>The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04</i> Vol.2: 694 - 696 {Cited by 1]<br/>

http://publicationslist.org/vadim.gektin/refid28 2013-02-21T02:50:53Z

Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than...<br/><br/>V. Gektin, D. Malladi (2004) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid29 2019-05-16T01:41:46Z

The present application describes a method and an apparatus for facilitating increased uniformity and diffusion of force transfer on a bare die electronic package for example, when such electronic package is attached to a circuit board. Additional force absorbent material is applied around a bare die in the bare die electronic package. The force applied to the bare die electronic package can be di...<br/><br/>V. Gektin, J. Jones (2004) <i>The United States Patent and Trademark Office (USPTO) [Cited by 2]</i><br/>

http://publicationslist.org/vadim.gektin/refid11 2019-06-14T23:28:28Z

Thermal design in electronic packaging is driven by the maximum allowable junction temperature of a CPU. An inadequate thermal design that underestimates the junction temperature may adversely impact the electrical performance of the CPU, making predicting the junction temperature a crucial step in package and system thermal design. A numerical model of a heat sink and thermal test package with a ...<br/><br/> Gektin, V. ; R. Zhang ; Vogel, M. ; Guoping Xu ; Lee, M. (2004) <i>The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04</i> Vol.1: 537 - 542 [Cited by 2]<br/>

http://publicationslist.org/vadim.gektin/refid20 2010-07-08T22:07:10Z

V Gektin (2004) <i>9th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electric Systems</i><br/>

http://publicationslist.org/vadim.gektin/refid21 2010-10-17T01:02:54Z

A Heydari, V Gektin (2003) <i>The Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference INTERpack03</i><br/>

http://publicationslist.org/vadim.gektin/refid26 2019-05-16T01:40:46Z

In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. An alignment tool is used to align the spacer with the silicon die. A thermal conductor can be placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A die interface material is not necessarily applie...<br/><br/>V. Gektin (2003) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid27 2013-02-21T02:54:07Z

In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. The thermal conductor is placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. ...<br/><br/>V. Gektin (2003) <i>The United States Patent and Trademark Office (USPTO)</i><br/>

http://publicationslist.org/vadim.gektin/refid1 2019-06-14T23:35:11Z

Thermal Interface Materials (TIMs) are used as thermally conducting media to carry away the heat dissipated by an energy source (e.g. active circuitry on a silicon die). Thermal properties of these interface materials, specified on vendor datasheets, are obtained under conditions that rarely, if at all, represent real life environment. As such, they do not accurately portray the material the...<br/><br/>V. Gektin, S. Ankireddi, J. Jones, S. Pecavar and P. Hundt (2003) <i> IPACK03- International Electronic Packaging Technical Conference & Exhibition, July 6-11, Maui, HI.</i> [Cited by 3]<br/>

http://publicationslist.org/vadim.gektin/refid25 2019-05-16T00:00:23Z

In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the p...<br/><br/>V Gektin, D Malladi (2003) <i>The United States Patent and Trademark Office (USPTO) [Cited by 1]</i><br/>

http://publicationslist.org/vadim.gektin/refid16 2019-06-14T23:45:37Z

In−plane temperature variations across a die, caused by the differences in power densities, have an adverse effect on the IC performance and reliability and could lead to functional failures. Elimination or, at least, reduction of in−plane temperature variations across the die, along with a decrease in junction temperature, is one of the most important tasks of thermal management in electronic...<br/><br/>V Gektin (2001) <i>The Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference INTERpack '01. IPACK2001, Kauai, HI, USA</i> 727 - 732<br/>

http://publicationslist.org/vadim.gektin/refid17 2010-07-18T18:21:14Z

Temperature variations on a die, caused by the differences in power densities, have an adverse effect on the package performance and reliability. Elimination or, at least, reduction of temperature variations on the die becomes one of the most important tasks of thermal design. Three possible solutions aimed at reducing temperature variations are evaluated. Thermal modeling of these solutions is pr...<br/><br/>V Gektin (2001) <i>Proceedings of FLUENT Users' Group Meeting, 2001, Sunnyvale, CA, USA [Unpublished]</i><br/>

http://publicationslist.org/vadim.gektin/refid5 2019-06-11T21:48:22Z

The continuing drive toward high-density, low-profile Integrated Circuit packaging has accelerated the spread of flip-chip technology to laminated substrates, creating direct chip attach (DCA) configurations. However, the substantial difference in the coefficients of thermal expansion (CTE) between the chip and the laminated substrates makes DCA configurations vulnerable to thermally-induced strai...<br/><br/>V. Gektin ; A. Bar-Cohen ; S. Witzman (1998) <i>IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A</i> 21: Issue: 4 577 - 584<br/>

http://publicationslist.org/vadim.gektin/refid4 2010-07-08T21:26:14Z

Due to the high I/O density, low-cost assembly, and low package profile, DCA is the technology of choice in many current applications. However, DCA configurations are vulnerable to thermally induced strains and the resulting solder-joint fatigue, which, in turn, leads to reduced reliability. In recent years it has been found possible to obtain dramatically higher (5-10X) reliability and to operate...<br/><br/> Gektin, V. ; Bar-Cohen, A. (1998) <i>Circuits and Devices Magazine, IEEE </i> 14: Issue:3 29 - 33<br/>

http://publicationslist.org/vadim.gektin/refid18 2019-06-15T00:01:52Z

The continuing drive towards high-density, low-profile Integrated Circuit packaging has accelerated the spread of flip-chip technology to laminated substrates, creating Direct Chip Attach (DCA) configurations. However, the substantial difference in the coefficients of thermal expansion (CTE) between the chip and the laminated substrates makes DCA configurations vulnerable to thermally-induced stra...<br/><br/>V. Gektin, A. Bar-Cohen and S. Witzman (1997) <i>The Pacific Rim/ASME International Intersociety Electronic & Photonic Packaging Conference, INTERpack '97</i> 1655 - 161<br/>

http://publicationslist.org/vadim.gektin/refid35 2019-06-17T23:53:23Z

V. Gektin (1997) <br/>

http://publicationslist.org/vadim.gektin/refid8 2010-07-08T21:44:07Z

The fatigue life of an underfilled flip-chip package has been evaluated using the Coffin-Manson relation and finite element modeling (FEM)-computed solder shear strain for typical flip-chip structures. In the course of this effort, numerical simulations were performed for underfill materials of varying thermo-structural properties, two chip sizes, and two solder bump heights. The results were used...<br/><br/> Gektin, V. ; Bar-Cohen, A. ; Ames, J. (1997) <i> IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A</i> 20: Issue:3 317 - 326<br/>

http://publicationslist.org/vadim.gektin/refid7 2010-07-08T21:45:07Z

Delamination and/or rupture of the die-attach layer are among the primary failure mechanisms in plastic IC packages and often lower the threshold for other mechanical, as well as electrical, failure mechanisms. Die-attach failure is generally caused by the thermal expansion (contraction) mismatch of dissimilar materials and the consequent development of axial and shear stresses in the adhesive and...<br/><br/> Gektin, V. ; Bar-Cohen, A. (1996) <i> I-THERM V., Inter-Society Conference on Thermal Phenomena in Electronic Systems, 1996</i> 306 - 313 [Cited by 12]<br/>

http://publicationslist.org/vadim.gektin/refid10 2010-07-08T21:45:45Z

The continuing drive towards high-density, low-profile integrated circuit packaging has accelerated the spread of flip-chip technology. The use of an area array of solder bumps for the electrical and mechanical, as well as thermal attachment of the chip to the substrate provides flip-chip technology with considerable advantages in cost, density, and electrical performance, relative to the use of c...<br/><br/> Gektin, V. ; Bar-Cohen, A. ; Witzman, S. (1996) <i>46th Electronic Components and Technology Conference, 1996</i> 440 - 447 [Cited by 5]<br/>

http://publicationslist.org/vadim.gektin/refid19 2010-07-18T18:20:49Z

V. Gektin and A. Bar-Cohen (1995) <i>Proceedings of 1st International Symposium on Advanced Packaging Materials, 1995, Atlanta, GA, USA [Unpublished]</i><br/>