Abstract: Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2, resulting in a significant I-ON boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for I-ON by 50%, maintaining similar I-OFF, as measured at the source.

Abstract: The effect of He/H-2 downstream plasma on chemical vapor deposition (CVD) low-k films with different porosities was studied. The results show that this plasma does not reduce the concentration of Si-CH3 bonds in the low-k matrix and that the films remain hydrophobic. However, mass loss and reduction in bulk C concentration were observed. The latter phenomena are related to the removal of porogen residue formed during the UV curing of the low-k films. It is demonstrated that the porogen residue removal changes the films' porosity and mechanical properties. The depth of the modification is limited by the penetration of H radicals into the porous low-k films.

Abstract: This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125 nm height which is used as a fin and a sloped bottom of 200 nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional alpha-C hard mask of 90 nm (with antireflective SiOC coating of 35 nm) on top of the STI stack (70 nm nitride on top of 8 nm oxide). The nitride layer and the top straight part of the fin is patterned using CH2F2/SF6/N-2 chemistry and alpha-C as a mask, while the bottom sloped part is patterned using Cl-2/O-2/N-2 chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged. (C) 2008 Elsevier B.V. All rights reserved.

Abstract: The role of plasma etching in the semiconductor technology upon switching from the microscale to the nanoscale dimensions is discussed. The continuing miniaturization has led to impossibility of simple scaling and further use of the conventional materials of silicon microelectronics. New materials and functional elements of integrated circuits call for revision of the existing plasma etching processes and development of novel processes. This situation brings plasma etching along with photolithography to the forefront of nanoelectronics technology.

Abstract: This letter reports on the implementation of high carbon content and high phosphorous content Si1−xCx layers in the source and drain regions of n-type MOSFET in a 65-nm-node integration scheme. The layers were grown using a novel epitaxial process. It is shown that by implementing stressors with x ≈ 0.01, nMOSFET device performance is enhanced by up to 10%, driving 880 μA/μm at 1-V VDD. It is also demonstrated that the successful implementation of Si1−xCx relies on the careful choice of integration and epitaxial layer parameters. There is a clear impact of the postepitaxial implantation and thermal treatment on the retained substitutional C content ([Csub]). Furthermore, adding a Si capping layer on top of the Si1−xCx, greatly improves upon the stressors’ stability during the downstream processing and the silicide sheet resistance.

Abstract: Titanium nitride (TiN) is widely used in metal gate applications. Exposing TiN to a Cl-2/HBr plasma results in pronounced surface roughness that can be easily characterized by ellipsometry. The ellipsometric angle Delta is proportional to the roughness if the roughness does not exceed 30 nm. It is possible to plot a "roughness diagram" where a border can be drawn between the smooth and rough etch surfaces depending on the etch conditions. This diagram could be used for gate-etch process optimization. In our case, the roughness could be overcome by increasing HBr content and/or substrate bias during the etching. (c) 2007 The Electrochemical Society.

Abstract: We propose a method for evaluating the hydrophilisation degree of low-k films upon plasma damage. The evaluation is based on optical emission spectroscopy analysis of O* emission during He plasma exposure of sample in question. The O* is presumably desorbed from damaged low-k film by vacuum-ultraviolet radiation from He plasma. The new method correlates well with other methods for plasma damage characterization such as Fourier Transform Infrared Spectroscopy and Water-Vapor Ellipsometric Porosimetry. The presented method gives a unique opportunity to assess the degree of hydrophilisation of low-k films immediately after processing. (C) 2008 Elsevier B.V. All rights reserved.

Abstract: We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 mn lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H-2 anneal) further reduce the CD to 13 nm. (c) 2007 Elsevier B.V. All rights reserved.

Abstract: The authors found that a BCl3/N-2 plasma is very suitable for metal gate patterning and profile control as it produces a passivating film during the etching. On blanket wafers, a boron-nitride-like film is deposited from. a boron trichloride/nitride plasma mixture in a standard etch chamber at temperatures as low as 60 degrees C. Deposition rate can be varied from 10 to more than 100 nm/min depending on the plasma conditions and BCl3/N-2 ratio. The film contains hexagonal boron nitride but is very unlikely to be a stoichiometric BN. It decomposes at elevated temperatures and is water soluble. The latter property makes the postetch clean relatively straightforward. This film can be used for sidewall passivation during the patterning of advanced non-Si gates, e.g., metal gates. They are presenting the use of BCl3/N-2 plasma for patterning of Ge and TaN gates as examples. The Ge gate profile is damaged,by a pure BCl3 plasma during high-k dielectric (HfO2) etching after the gate patterning. Addition of 10% N-2 to the BCl3 plasma preserves the gate profile while removing the high k. In the other example, a TaN gate is etched isotopically by pure BCl3 plasma. Addition of 5% N-2 prevents the lateral attack providing straight TaN profile. (c) 2007 American Vacuum Society.

Abstract: Porous films are used nowadays as dielectrics with low dielectric constant (so-called low-k dielectrics). Knowing the porous structure of such films is important for successful integration in the semiconductor manufacturing technology. We developed a simple characterization method based on diffusion of solvents inside a porous film. In our experiments toluene as a non-polar solvent and ethanol as a polar solvent were used. A porous film is covered with a barrier impermeable for solvent so the solvent only can enter the film from the side. The barrier is transparent that allows observation of diffusion as a color change of the film. Measuring diffused distance as a function of diffusion time, diffusion coefficients can be calculated. It was found that the diffusion coefficients strongly depend on the porous structure of the films. Small pores (with the size comparable with the solvent molecule size) show low diffusion coefficients with high activation energies comparable with the enthalpy of evaporation. Bigger pores exhibit high diffusion coefficients with low activation energies corresponding to the activation energy of the solvent viscosity. Measuring diffusion coefficients as functions of porosity/pore size it is possible to evaluate the interconnectivity of the porous structure of a film in question. (C) 2006 Elsevier B.V. All rights reserved.

Abstract: Recessed strained SiGe in the source/drain regions of planar Si pMOS devices is a well-known technique to enhance pMOS drive current. Both chemical vapour etching by HCl and conventional plasma etching have been proposed to define the source/drain recess. A comparison of both etching techniques brings us to the conclusion that isotropic plasma etching is the preferred etching technique. It avoids problems of facet formation during Si recess and allows better control of the lateral etching underneath the nitride spacer/gate oxide. Further, process optimization allows to minimize the variation in etch depth as function of window size. Surface damage caused during Si recess is removed by conventional cleans. High quality in situ doped SiGe layers, with boron concentrations up to similar to 4 x 10(20) cm(-3) are grown, without modification of our standard pre-epi thermal treatments. The success of our SiGe source/drain fabrication scheme is demonstrated by a 40% improvement in pMOS drive current in comparison to Si reference devices. (c) 2005 Elsevier B.V. All rights reserved.

Abstract: The etch properties of physical vapor deposited TaN used as a metal gate electrode have been found to be dependent on its crystalline microstructure. As found by X-ray diffraction, the initially amorphous TaN crystallizes at temperatures above 500 degrees C. The crystallization results in lower resistivity (decreased by 13%), and lower etch rate in BCl3 plasma (decreased by 24%). The different crystalline microstructure can manifest itself in different etch results when the same etch process is applied for gate stacks that contain the same TaN but were subjected to different thermal budget. (c) 2006 The Electrochemical Society.

Abstract: A study of the impact of physical vapor deposition conditions on the etch properties of TiN has been conducted using a transformer coupled plasma. This work focuses only on a Cl-2-based etch plasma. It is shown that the crystallographic orientation of TiN, observed from x-ray diffraction spectra, has a major influence on the etch behavior. Etch yields at varying dry etch conditions of two types of TiN, with different crystallographic orientations, have been studied quantitatively. The high roughness which is created during plasma exposure was identified as being the result of different etch rates of grains and intergranular material at the grain boundaries. Moreover, it is shown that TiN(111) is more difficult to etch, resulting in more pronounced roughness, than TiN(200), which is easier to etch, resulting in smoother surfaces for certain process conditions. (c) 2006 American Vacuum Society.

Abstract: Among the pretreatment methods which are performed just after the lithographic process to minimize the roughness increase of 193 nm photoresist during the subsequent etching processes, an in situ plasma pretreatment is the most cost effective. A HBr plasma pretreatment has proven quite effective and a few papers have described the mechanism. In an effort to understand further, the authors evaluated four plasma pretreatments using HBr, Ar, H-2, or Cl-2 gases and,compared their results. Fourier transform infrared (FTIR) spectroscopy was performed for the investigation of the chemical changes effected by the plasma pretreatments. Cross-section scanning electron microscope (SEM) images were used to measure the photoresist film thickness, while top-down SEM images and an off-line program were used to determine linewidth roughness (LWR) changes for 70 and 80 nm line features. They found two different types of roughness. The first type is a low-frequency roughness, which repeats about every 400 nm and increases the LWR value substantially. The second type is a high-frequency roughness, which appears about every 100 urn and causes a moderate increase in the LWR value. From the top-down SEM images, they recognize that the low-frequency roughness is caused by collapse of the 193 nm photoresist during the following bottom antireflective coating and hard-mask etching processes. The no plasma and the Ar plasma pretreated samples show this low-frequency roughness and produce the worst LWR values of about 11 nm at the 70 nm linewidth features after ashing processes. The HBr and the H-2 plasma pretreated samples, which mainly show the high-frequency roughness, result in the best LWR values of about 6 nm at the 70 urn linewidth features after ashing processes. The FTIR analysis shows that both the HBr and H2 plasma pretreatments reduce the CO content substantially, down to about 20%-40% of the original CO content of the 193 nm photoresist as-coated film. On the other hand, the Ar plasma pretreated photoresist film still has about 60% of the CO content of the pristine 193 nm photoresist. The authors conclude that the low-frequency roughness has a critical relationship with the CO content in the 193 nm photoresist. They also find that the elements being incorporated into the 193 nm photoresist during the plasma pretreatment are important for their impact on the LWR. Especially, the Cl-2 plasma pretreatment, which eliminates about the same amount of the original CO content in the photoresist as both the HBr and H-2 plasma pretreatments, deteriorates the LWR notably just after the pretreatment and produces the most severe deformation after etching processes. Of the plasma pretreatments evaluated in this work, the HBr plasma pretreatment is the best in view of both the LWR and the application. The H2 plasma pretreatment, which shows the same lowest LWR value as the HBr plasma pretreatment, reduces the photoresist thickness substantially. However, even the HBr plasma pretreatment has one critical disadvantage because it generates the high-frequency type of roughness, which is not found in the case of the inert Ar plasma pretreatment. The H and Br radicals react with the 193 nm photoresist during the HBr pretreatment and appear to cause some side reactions and generate the high-frequency type of roughness during subsequent plasma processes. To minimize both the low- and high-frequency deformations simultaneously, we propose an inert gas plasma pretreatment process of which process parameters such as pressure nd power are optimized to reduce the CO content of the 193 nm photoresist less than 40% of the original CO content as coated. (c) 2006 American Vacuum Society.

Abstract: During Ru etch with oxygen-based plasma, strong emission lines have been observed in the region of 340-390 nm with the most prominent peak at 373 nm. These are attributed to the emission of neutral Ru. We have shown that the emission can be used for end-point detection for Ru patterning by plasma etch as well as for highly sensitive in situ monitoring of the etch chamber cleaning after Ru processing. (c) 2005 The Electrochemical Society.

Abstract: We report on gate patterning development for the 45 nm node and beyond. Both poly-Si and different metal gates in combination with medium-k and high-k dielectrics have been defined. Source/drain silicon recess has been characterized for different stacks, yielding optimised processes for all investigated. Using hardmask based etching allowed us to produce sub-20 nm poly-Si and metal gates. Implementation of advanced metal gate patterning in already developed multigate field effect transistors (MuGFET) devices has been demonstrated. (c) 2004 Elsevier Ltd. All rights reserved.

Abstract: In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 10(10) at/cm(2).

Abstract: Oxide hard mask was found to have a profound effect on sub-100 nm Si and SiGe gates profiles. The gates patterned with hard mask only (photoresist is stripped after hard mask patterning) exhibit considerable profile distortion. It has been found that the distortion is caused by the ions deflection due to the charge accumulation on the hard mask. The distortion can be avoided by using either a thinner (15 nm-20 nm) hard mask (that accumulates less charges) or by increasing the ion energy, using higher (above 150 W) bias power (ions impinging the surface with higher speed are less likely to be deflected). (c) 2005 American Vacuum Society.

Abstract: Atomic layer deposition (ALD) of tungsten carbide nitride (WC0.7N0.3) on a low-k (dielectric constant) dielectric aromatic polymer material is investigated. It is feasible to deposit thin WC0.7N0.3 films on polymers, but applying a nitrogen-oxygen (N-2-O-2) based plasma to the surface prior to ALD can significantly enhance the growth. The creation of polar surface groups by the plasma treatment is derived from the water contact angle and from O 1s to C 1s peak ratio extracted from x-ray photoelectron spectroscopy. Rutherford backscattering spectra and contact angle measurements revealed a typical ALD growth with at least two successive regimes. The first is controlled by the substrate surface, while during the last a constant amount of ALD material is added with each cycle. The plasma treatments create adsorption sites on the surface and therefore effectively enhance the growth and shorten the duration of the first regime. This observation is attributed to an improved initial ALD precursor adsorption. However, ALD island formation on the treated polymer is not merely a function of the number of available adsorption sites but depends also on the structure and composition of the substrate surface. The minimum thickness of a continuous ALD film is similar to10 nm on untreated polymer while on top of a N-2 rich reactive ion etch plasma-treated polymer the WC0.7N0.3 film becomes continuous between 1.4 and 2.3 nm. (C) 2004 American Institute of Physics.

Abstract: Performance improvements in microelectronic integrated circuits (ICs) over the past few decades have, for the most part, been achieved by increasing transistor speed, reducing transistor size, and packing more transistors onto a single chip. Smaller transistors work faster, so ICs have become faster and more complex. An emerging factor that may disrupt this trend is the slowing speed of signal propagation within the chip. Signal delays, caused by the interconnection wiring, increase with each generation of scaling and may soon limit the overall performance of the integrated system.

Abstract: The pore connectivity threshold (percolation threshold) in porous low-K dielectric films measured by Positron Annihilation Lifetime Spectroscopy (PALS) reflects only the interconnectivity of mesopores (2-50 nm size). Here we show direct evidence for molecular (toluene) diffusion at porosity values significantly below the PALS's percolation threshold. Therefore, the pores are still interconnected through intrinsic micropores (<2 nm) in the low-K film matrix. This implies that fundamental limitations may exist in the evaluation of pore interconnectivity and the integrity of diffusion barriers deposited on top of porous low-K films by the detection of Ps escape.

Abstract: In order to reduce resistance and capacitance copper wiring is used along with materials possessing a low dielectric constant (low-k materials). A diffusion barrier is used in Cu/low-k integration scheme to prevent Cu diffusion into low-k materials. A film integrity evaluation method is needed for barrier characterization. The method should be able not only to test the barrier integrity but also to find low-density defects (so called "killer defects"). We propose fast, simple, and accurate evaluation of diffusion barriers by ellipsometric porosimetry (EP). This method can be used for testing barriers with respect to solvent penetration. When a barrier contains pores,,an adsorptive (toluene) penetrates through. these pores and condenses in the low-k dielectric film (e.g., porous glass or organic polymer). The condensation changes optical characteristics of the low-k film that is measured by EP. Low-density killer defects are visualized by toluene trapped around the defect beneath the barrier. We have evaluated a Ta(N) barrier on a porous glass and a WCN barrier on an organic polymer low-k films. Our experiments show that EP is able to test barrier integrity and find killer defects. If a barrier deposited on a porous film is noncontinuos, then EP is able to determine barrier optical constants and thickness as well as to estimate barrier porous structure. (C) 2003 American Vacuum Society.

Abstract: The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the characteristics and properties of low-k dielectrics. In addition it addresses some of the needs for improved metrology for determining pore sizes, size distributions, structure-and mechanical properties. (C) 2003 American Institute of Physics.

Abstract: As an interconnect material, copper has the disadvantage of not forming self-limiting oxides, which can negatively affect device performance and reliability. Undesired oxide layers need to be removed by in situ cleaning, before the copper is subjected to subsequent depositions. We have used ethyl alcohol (C2H5OH) as a vapor phase reducing agent to remove copper oxides formed on electroplated copper films upon exposure to the ambient. Spectroscopic ellipsometry has been used to monitor the reduction process in situ. Ex situ characterization using X-ray photoelectron spectroscopy and atomic force microscopy support in situ measurements. While oxide removal can be achieved at temperatures as low as 130degreesC, independent of oxide layer thickness and composition, it occurred more efficiently at 200degreesC, showing compatibility with the low temperature (<400&DEG;C) processing requirements of low dielectric constant materials. The initial reaction involves the reduction of Cu2+ to Cu+ species followed by a second phase consisting of Cu+ conversion to elemental copper, producing a clean metal surface. Reduction of Cu2+ to Cu+ species is the rate-limiting step as evidenced by enhanced sensitivity to the reaction temperature. (C) 2003 The Electrochemical Society.

Abstract: Porous glasses are widely used in microelectronics as inter-metal dielectrics with low dielectric constant (so-called low-k dielectrics). At the same time copper is used as a metal because of its low resistivity. Combination of Cu and low-k requires a barrier to prevent Cu diffusion into a low-k dielectric. Integrity of such a barrier becomes an issue when porous glass is used as a low-k dielectric. The barrier should be as thin as possible and fully dense at the same time. Using solvent (toluene) penetration through a barrier (tantalum nitride in our case, which is non-stoichiometric, hence denoted as Ta(N)) and adsorption in porous glass as a barrier integrity probe, we show that barrier integrity depends not only on porous structure of the glass, but also on its chemical composition (namely on carbon content). Glasses with high carbon content are easier to seal with Ta(N) barrier. With help of Monte Carlo simulations, we speculate that different chemical composition of the porous glass results in different surface diffusion during barrier deposition. Different surface diffusion, in turn, results in different integrity of the porous barrier.

Abstract: Evaluation of diffusion barrier integrity is an important issue in advanced interconnects. A diffusion barrier separating Cu from low-k must be as thin as possible and must not contain pinholes. We have developed a method for measuring pinhole density in diffusion barriers deposited on low-k materials. The method employs ellipsometric porosimetry for measuring diffusion of toluene in a porous low-k film beneath the barrier in question. (C) 2003 Elsevier B.V. All rights reserved.

Abstract: Implementation of Cu/low-k in advanced interconnections requires a diffusion barrier to prevent copper penetration in low-k dielectrics. The barrier should be continuous to prevent copper diffusion and thin enough to keep interconnection line resistance low. Deposition of a diffusion barrier becomes an issue when porous low-k dielectrics are used. We developed a Monte Carlo simulation model to describe deposition of a diffusion barrier on a porous low-k film. The model provided explanation for the sealing behavior of different porous film by TaN diffusion barrier. Previously we have shown that TaN barrier integrity depends on chemical nature of the substrate rather than on porous structure: the same barrier can be continuous on oxycarbide (SiOCH) but non-continuous on HSQ (hydrogen silsesquioxane) although porous structures of the two films are similar. Using the model, we show that surface diffusion of TaN during deposition plays a key role in continuous barrier formation. Presence of carbon suppresses TaN diffusion (probably by TaC formation) and the barrier does not penetrate deep into the film forming a continuous layer on the top surface. The model is also able to predict sealing behavior for different porous low-k films with different porosity/pore sizes. (C) 2003 Elsevier B.V. All rights reserved.

Abstract: The interaction between conventional and highly porous SiOCH with CF4, O-2, and H-2 plasma has been investigated. The highly porous SiOCH film has porosity about 40% and a k value about 2.2. The pristine SiOCH film has 19% of porosity and k value of 2.7. All experiments were performed at room temperature in a downstream plasma reactor. It was found that (i) the CF4 plasma etches the SiOCH film without bulk material modification (however, the etch rate was higher in the case of the SiOCH film with increased porosity); (ii) the O-2 plasma oxidizes the SiOCH film converting the top layer to a hydrophilic SiO2-like porous material, the SiOCH film with increased porosity suffers more severely from this kind of plasma; (iii) the CF4/O-2 plasma mixture has an optimal O-2 concentration at which the etch rate is maximal; and (iv) the H-2 plasma does not interact with the SiOCH film and can be a promising candidate for the resist stripping. (C) 2002 American Vacuum Society.

Abstract: The deposition of homogeneous thin films on porous substrates has been investigated. The thin film deposition of Ta(N) by physical vapor deposition on porous films with different average pore sizes and material compositions has been studied. The continuity of Ta(N) films on top of porous low-k dielectrics is evaluated by means of ellipsometric porosimetry combined with sheet resistance and atomic force microscopy measurements. Interface reactions are analyzed by x-ray photoelectron spectroscopy profiling. It has been observed that the minimal Ta(N) thickness required to obtain a continuous metal layer on top of the porous film depends, on the one hand, on the porosity and pore size and, on the other hand, on the chemical interaction of the thin film with the porous substrate. The sealing of pores is favored by the presence of carbon in the dielectric matrix. This is explained through a mechanism of local enhancement of the degree of crosslinking in the dielectric matrix, catalyzed by Ta. (C) 2002 American Institute of Physics.

Abstract: Four CVD SiOCH films deposited at various conditions were used for comparative evaluation. The films were evaluated by RBS, spectroscopic ellipsometry, and ellipsometric porosimetry. Oxygen plasma resistance was studied by spectroscopic ellipsometry and TOF-SIMS analysis after exposure of the films to downstream oxygen plasma. The different deposition conditions result in different carbon content and different porosity. The film with the highest carbon content has the lowest porosity and vice versa. As carbon content of films increases and their porosity decreases, the SiOCH films become more resistant to oxygen plasma. (C) 2002 Elsevier Science B.V. All rights reserved.

Abstract: Galvanic corrosion of copper as a function of barrier metal type together with the effect of acid type is investigated. Refractory metals such as Ta, Ti, and W are used as the barrier metals. HNO3-based and H2O2-based aqueous solutions are used to analyze the effect of acid type of the CMP slurry on the galvanic corrosion. The results show that the galvanic etch rate of copper is affected by the barrier metal type. In addition, the type of solution used is found to influence the barrier metal as well as the copper. Especially for the case of W, the change in the direction of the electrical current flow between copper and the barrier metal depending on the type of solution used seems to alter the galvanic reaction mechanism. (C) 2002 Elsevier Science B.V. All rights reserved.

Abstract: A method for controllable increase of porosity of low-k silicon oxycarbide films (SiOCH), deposited by oxidation of 3-methylsilane, has been developed using etching of the SiOCH film by diluted HF solution. The modified SiOCH film is characterized by Fourier transform infrared spectroscopy, X-ray photoelectron spectrscopy, and ellipsometric porosimetry. It is found that the chemical composition of the modified SiOCH film remains almost the same during etching. No significant thickness loss is observed, while the pore radius and the film porosity increase with HF dip time. It was concluded that the increase of the pore radius is caused by isotropic etching inside the pores as well as at the film surface. The very low etch rate of SiOCH film by diluted HF and the large difference between the pore radius and the film thickness allows an increase in the porosity without significant thickness loss. This method is a way to prepare ultralow-k dielectric films with higher chemical stability as compared to oxide and silsesquioxane-based porous materials. (C) 2000 The Electrochemical Society. S1099-0062(00)08-010-X. All rights reserved.

Abstract: A novel method for controllable increase of porosity of low-k silicon oxycarbide films (SiOCH hereafter) deposited by oxidation of 3-methylsilane has been developed. The etching of the SiOCH film by diluted HF solution has been used for this purpose. The modified SiOCH film is characterized by FTIR, XPS, TDS and EP. It is found that the chemical composition of the modified SiOCH film remains the same during the etching. No significant thickness loss is observed, while the pore radius and the film porosity is increasing with HF dip time. This method is considered as a way to prepare ultra low-k dielectric films with quite high chemical stability.

Abstract: When a Cu surface is exposed to a clean room ambient, a surface layer containing Cu2O, CUO, Cu(OH)(2), and CuCO3 is formed. Thermal treatment in a vacuum combined with hydrogen plasma can remove this layer. Water and carbon dioxide desorb during the thermal treatment and the hydrogen plasma reduces the remaining Cu oxide. Ellipsometric, x-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectroscopy analyses indicate that the mechanism of interaction of the H-2 plasma with this layer depends on temperature. When the temperature is below 150 degreesC, H-2 plasma cannot completely reduce Cu oxide. Hydrogen diffuses through the oxide and hydrogenation of the Cu laver is observed. The hydrogenated Cu surface has a higher resistance than a nontreated Cu layer. The hydrogen plasma efficiently cleans the Cu surface when the substrate temperature is higher than 150 degreesC. In this case, hydrogen atoms have enough activation energy to reduce Cu oxide and adsorbed water forms as a byproduct of Cu oxide reduction. When the wafer temperature is higher than 350 degreesC, the interaction of the Cu film with hydrogen and residual oxygen is observed. (C) 2001 American Vacuum Society.

Abstract: The objective of this study was silicon surface cleaning after high-density plasma dry etching. The cleaning after oxide spacer etching was investigated. XPS and ellipsometry analysis were together used to estimate surface cleanness after various cleaning procedures. It was found that silicon surface is seriously damaged during the plasma etching and can be restored by Ar+ beam treatment. A model was developed to describe different cleaning steps needed for full clean after plasma etching.