Abstract: We present a schema to build one way functions from a family of Boolean gates. Moreover, we relate characteristics of these Boolean gate truth tables to properties of the derived one-way functions. We believe this to be the first attempt at establishing cryptographic properties from the Boolean cube spaces of the component gates. This schema is then used to build a family of compression functions, which in turn can be used to get block encryption and hash functions. These functions are based on reconfigurable gates. We prove cryptographically relevant properties for these function implementations. Various applications incorporating these one-way functions, specifically memory integrity in processor architecture, are presented.
Abstract: The increasing sub-threshold leakage current levels with newer technology nodes has been identified by ITRS as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size. This results in ever-increasing power per unit area and the accompanying problem of heat removal and cooling. Portable battery-powered applications, fuelled by pervasive and embedded computing, in the last few years have seen a tremendous growth and have reached a point where battery power can't be increased further. This raises the computational throughput per watt target for the future technology nodes. SRAM arrays which are used widely as a system component, such as caches and register files, in both high-performance and portable systems, are getting to be dominant power consumers because of their large capacity and area. Hence any reduction in cache energy can result in considerable overall power reduction. In this paper, we propose a novel circuit technique using depletion mode devices, to reduce the static energy of SRAM array in an on-chip cache by 90% without any performance impact.
Abstract: Software obfuscation is defined as a transformation of a program P into T(P) such that the whitebox and blackbox behaviors of T(P) are computationally indistinguishable. However, robust obfuscation is impossible to achieve with the existing software only solutions. This results from the power of the adversary model in Digital Rights Management systems, which is significantly more than in the traditional security scenarios. The adversary has complete control of the computing node—supervisory privileges along with the full physical as well as architectural object observational capabilities. In essence, this makes the operating system (or any other layer around the architecture) untrustworthy. Thus, the trust has to be provided by the underlying architecture. In this paper, we develop an architecture to support 3D obfuscation through the use of well-known cryptographic methods and show how it provides copy-protection, IP-protection, and tamper-resistance.
Abstract: REBEL is a fiestel network based block encryption function which uses reconfigurable gates instead of substituition
boxes. This novel design approach has many advantages such as the key size can be much greater than
the block size, security can be reduced to boolean square root problem (Kutz, 2004) and resitant to known
cryptanalytic attacks. The implementation results show that our proposed design can better AES in every
design parameter at the same time providing much higher security.
Abstract: We present a schema to build one way functions from a family
of Boolean gates. Moreover, we relate characteristics of
these Boolean gate truth tables to properties of the derived
one-way functions. We believe this to be the first attempt
at establishing cryptographic properties from the Boolean
cube spaces of the component gates. This schema is then
used to build a family of compression functions, which in
turn can be used to get block encryption and hash functions.
These functions are based on reconfigurable gates.
We prove cryptographically relevant properties for these
function implementations. Various applications incorporating
these one-way functions, specifically memory integrity
in processor architecture, are presented.
Abstract: We are moving towards the era of pervasive computing. The embedded computing devices are everywhere and they need to interact in many insecure ways. Verifying the integrity of the software running on these devices in such a scenario is an interesting and difficult problem. The problem is simplified if the verifying entity has access to the original binary image. However, the verifier itself may not be trusted with the intellectual property built into the software. Hence an acceptable and practical solution would not reveal the intellectual property (IP) of the verified software, and yet must verify its integrity. We propose one such novel solution, TIVA, in this paper.
Abstract: In DRM domain, the adversary has complete control of the computing node - supervisory privileges along with full physical as well as architectural object observational capabilities. Thus robust obfuscation is impossible to achieve with the existing software only solutions. In this paper, we develop architecture level support for obfuscation with the help of well known cryptographic methods. The three protected dimensions of this architecture Arc3D are address sequencing, contents associated with an address, and the temporal reuse of address sequences such as loops. Such an obfuscation makes the detection of good tampering points infinitesimally likely providing tamper resistance. With the use of already known software distribution model of ABYSS and XOM, we can also ensure copy protection. This results in a complete DRM architecture to provide both copy protection and IP protection.
Abstract: The increasing sub-threshold leakage current levels with newer technology nodes has been identified by ITRS [1] as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size. This results in ever-increasing power per unit area and the accompanying problem of heat removal and cooling [2]. Portable battery-powered applications, fuelled by pervasive and embedded computing, have seen tremendous growth and have reached a point where battery energy and power density can’t be increased further [3]. This raises the computational throughput per watt target for the future technology nodes. SRAM arrays which are used widely as a system component, such as caches and register files, in both high-performance and portable systems, are getting to be dominant power consumers because of their large capacity and area. Hence any reduction in cache energy can result in considerable overall power reduction. In this paper, we propose a novel circuit technique using depletion mode devices, to reduce the static energy of SRAM array in an on-chip cache by 90% without any performance impact.
