Abstract: A fully analytical steady state solution is presented for the problem of 3-D conjugate heat transfer in flip chip electronic packages with multiple general areal power sources, cooled by heatsinks using forced convection. The inherent simplicity of the proposed approach allows for expedient yet detailed package cooling/thermal analysis and evaluation of what-if scenarios while requiring only modest computational resources such as a personal computer. The soundness of the approach presented is demonstrated via excellent correlation with the results of experimental tests on flip-chip thermal test packages in a wind tunnel. The techniques developed herein are fairly general and can be readily adapted to other package designs wherein the primary heat transfer path is through the die, die-lid interface, lid, lid-sink interface and heatsink to the airflow through the fins.
Abstract: Three passive damper configurations are studied for buildings: unidirectional dampers oriented to the story principal axes and dampers with a single mass attached to spring-dashpot elements laid out at 90°/120° to each other. A simple damper design procedure to minimize a weighted combination of RMS building responses, using the concept of structure-constrained feedback control, is presented. Examples of six tall buildings with roof dampers and various plan geometries are considered. Performance of the simple dampers under along/across wind loads and seismic excitation are studied. With varying loading direction, unidirectional dampers show differing levels of control performance; however, performance of the latter types of dampers appears independent of excitation direction. For multi-winged buildings a good damper seems to be a single mass connected to one set of spring-dashpot elements for each wing; for wings exactly or nearly aligned with each other, a single spring-dashpot unit in one of them appears sufficient. Numerical results for performance and effectiveness of the dampers are presented and discussed.
Abstract: A control methodology is presented for a column, modeled as a single-degree-of-freedom system subjected to simultaneous horizontal and vertical support motion. It is assumed that the support motions are uncertain , time varying, and norm bounded and that the column itself has no uncertainties associated with it. The control signal is based on Lyapunov theory and noise-free state feedback measurements. The states of the resulting closed-loop system (namely displacement and velocity) are uniformly and ultimately bounded within a neighborhood of the zero state. To illustrate the features of the proposed controller, examples of nonhysteretic and hysteretic columns subjected to combined horizontal and vertical nonstationary seismic excitation are considered. Numerical results for the uncontrolled and controlled responses are obtained and analyzed. Several issues involved in the controller design are examined, and results illustrating the control performance and effectiveness are presented and discussed.
Abstract: An optimal control method involving sampled data is considered for use in earthquake and wind engineering applications. The structure is modelled as a continuous system attached to a discrete-time controller using zero-order sample-and-hold devices. Examples of two buildings with active base isolators and a 163 m tall planar frame with an active mass damper are considered. The buildings with the base isolators are subjected to excitation input using the 1940 El Centro earthquake (NS component) as an example, while the planar frame is subjected to assumed sinusoidal gusts with a period close to that of the frame. The controlled responses (with and without time delays) are studied. To further analyze the features of the control designs, the building examples with base isolators are subjected to five other different earthquake excitation records. Trends in control performance and effectiveness are presented and discussed. The results suggest that such systems are potentially suited for implementation in the vibration control of civil infrastructures; such potentiality becomes more realistic with the current trends in software development and the increased use of digital computers.
Abstract: A simple algorithm for multiobjective linear quadratic Gaussian control that can be used for various structural control applications is presented. This algorithm synthesizes Pareto optimal trade-off curves, which are plots of one performance variable constraint versus another. These curves separate the regions of feasible and infeasible constraints and enable the control designer to minimize one regulated output, such as control force, a structural displacement, or an acceleration, while keeping others within specified constraints. Pareto optimal curves are compared with each other to determine preferred locations for actuators and/or sensors. To illustrate the proposed methodology, numerical examples of simple lumped-mass shear-beam building models subjected to stochastic wind and earthquake loads are considered. Control is presumably through one or more active tendons placed on various floors of the structure. The numerical results presented demonstrate the applicability and feasibility for developing optimal multiobjective controllers for civil structures.
Abstract: Two neural network architectures are proposed for use in structural control applications: a Failure Detection Neural Network and a Failure Accommodation Neural Network. The Failure Detection Network monitors structural responses and automatically detects sensor failures that can reduce control performance and effectiveness, while the Failure Accommodation Network accounts for the failed sensors. Together, the networks are a step toward development of an expert diagnostic system for structural applications. Examples of two simple structures are used to illustrate the features of the networks. Sensor failures are simulated during control operation, and the ability of the networks to detect and accommodate the failures is examined. The numerical results reveal that these networks show promise for automated intelligent fault detection, identification, classification, and accommodation, and as such may have potential use in real civil structures. Although the networks have been used to detect and account for sensor faults alone, they may also be trained for other kinds of failures. Thus, they have potential for incorporation into an intelligent structural monitoring system.
Abstract: Seismic activity and wind loads cause significant losses to life, property and infrastructural facilities. Research in civil structural control is aimed at improving the safety and reliability of these facilities by reducing the hazardous responses caused by such natural phenomena. In this context, a capsule of recent collaborative efforts by the authors, aimed at developing passive/active control devices and control algorithms, is presented. Among the techniques considered here are designs of active mass dampers for wind and seismic excitation, multiobjective control, specialized passive damper design, and sampled data stepped control. For the active mass dampers, simplified structural models are used to obtain analytic design parameters. In the multiobjective control method reviewed, a technique to synthesize a structural controller (such as an active tendon) capable of satisfying several simultaneously imposed design criteria is presented. The specialized passive dampers reviewed here have been shown, in simulation studies, to be effective in reducing vibration levels for all incident excitation directions. The stepped digital control technique discussed is potentially suited for implementation in civil infrastructural systems, especially with increasing use of digital computers and software trends. Selected numerical results, illustrating control performance and effectiveness, are presented for these approaches.
Abstract: A procedure for the design of controllers for tall buildings under wind loads is presented. It is assumed that there are constraints on the design, in terms of requiring that the root-mean square (RMS) values of certain displacements, velocities, or accelerations be within prescribed values. In addition, there are constraints on the RMS control force available. Under these conditions, the synthesis of a stabilizing controller is investigated. The solution process involves posing the search for a controller as a problem of constrained optimization for which the Lagrange multipliers are determined by an ellipsoid algorithm. These multipliers are directly related to the weights in the objective function of an associated Linear Quadratic Gaussian (LQG) optimal control problem. Thus the design problem may be seen to be one of optimal weight selection in the LQG setting. Two examples of tall buildings under wind loads, involving the design of active tuned mass dampers, are considered to illustrate the design process and to assess the performance of the controllers. Results on the performance of the designs and the control effectiveness are presented and discussed. The generality of the current procedure enables it to be applied directly to other kinds of structures like bridges, shell-like domes, cooling towers, tall chimneys, under earthquake or wind loads, and using either active mass dampers, active tendon control, or other techniques as appropriate.
Abstract: A procedure for the design of a second-order dynamic controller is presented. The proposed method is applied to the control of structures under earthquake and wind excitations. The controller gains are determined by minimizing the root-mean-square value of the response parameter of interest for the structure, assuming that the excitation is Gaussian white noise. Three examples of structures (of which two are assumed to be subjected to the N-S component of the 1940 El Centro earthquake and one is assumed to be excited by wind loads) are considered to illustrate the design technique. In the first of the earthquake engineering applications, the controller is used for active base isolation of a building modeled as a shear frame, while in the second, it is used to develop an active mass damper for a three-dimensional building with eccentric axes of inertia and rotation (and consequently coupled longitudinal, lateral, and torsional motions). The wind engineering application is the design of an active mass damper for a high-rise building modeled as a planar frame subjected to wind loads. Numerical results for the examples reveal that the actively controlled base-isolation system with velocity feedback has better performance than that with either acceleration or displacement feedback. Complete feedback (i.e. feedback using position, velocity, and acceleration) was used for the active mass damper designs, and the controller was seen to be quite effective in reducing displacement and acceleration levels for both the three-dimensional building (with various eccentric locations of the axes of rotation and inertia) and for the planar frame. For all examples studied the active control systems were observed to perform better than their passive counterparts. Comments on the performance and control effectiveness of these designs and closed-loop-system behavior are made.
Abstract: A procedure for the design of an active tuned mass damper for vibration control in tall buildings subject to wind loads is presented. The building motions are modeled by the first mode of the response, and it is assumed that the excitation is white noise. The controller is based on complete feedback (namely, feedback of displacement, velocity, and acceleration). The controller gains that minimize the variance of the rooftop displacement are derived in closed-form. Two examples, one of a 162 m tall planar frame and the other of a 400 m tall building in a city are studied to illustrate the active damper design and to evaluate the procedure and the results. The same examples are then studied as multiple-degree-of-freedom systems subject to nonwhite excitation that better simulates the wind. Results on the reduction of the dynamic response and control effectiveness of the active damper designs are presented and discussed.
Abstract: With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common theme in next-generation CPU offerings will be the use of Dynamic Voltage and Frequency Scaling(DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.
Abstract: The capability and diversity of high performance microprocessors is increasing with each process technology generation in order to meet increasing application demand. The cooling designs for these electronic chips have to deal with larger temperature gradients across the die than previously. The key to thermal management is to dissipate the thermal energy from a heat-generating device to a heat sink via conduction through a thermal interface material (TIM). The TIM must also relieve the mechanical stress and absorb strain caused by coefficient of thermal expansion (CTE) mismatch between heat spreader lid and silicon die during field operation. Low modulus TIM is excellent at strain absorption and relieves stress from CTE mismatch of different materials. In this study we explore the fluxless bonding of indium as a candidate TIM for high performance microprocessors due to its high thermal conductivity, low melting temperature and low tensile strength and its green-ness (non-hazardous material, minimal waste and ease of product reworkability). Challenges in the development process include: controlling bond line thickness, fillet extent and controlling voids in the TIM assembly at reflow temperatures. This paper aims to investigate these key challenges and provide some general recommendations.
Abstract: In 2008 the Semiconductor Packaging group at Sun Microsystems published a technique for rapid thermal
mapping of flip chip microprocessor/ASIC packages using analytical spectral superposition techniques. The
primary focus of the current paper is to introduce a 100% pure Java application called HotPak, which embodies
the analytical/computational engine from that paper, and to describe its multitude of features. HotPak has
impressive benchmarks- on a typical laptop computer it takes less than 5 mins to do a complete thermal
simulation for a microprocessor/ASIC layout with 10,000+ blocks. Since it is written in Java, it works flawlessly
on Windows, Linux and MacOS. The predictions from the underlying engine have been verified experimentally
via rigorous testing.
Abstract: As process technology continues to evolve, gate sizes in today's microprocessors continue to shrink with each lithography generation. Accompanying these shrinks is a notable increase in the power dissipated by the various blocks and sub-blocks on the die. While the increased power is a challenge to the cooling design in its own right, another significant aspect that the thermal design engineer must keep in mind is that the distribution of power on the die (silicon) can vary dynamically depending on the software application that is running. As multi-core, multi-threaded chips become more prominent, these problems are compounded even further. Each core of the chip is capable of running independent threads supporting the software applications, and the resulting die power distribution can be significantly 'non-uniform' in real time. As such, it becomes all the more imperative to study the effects of such power non-uniformity on the microprocessor cooling capability. There is another aspect of package cooling analysis which is traditionally ignored, and that is the part-to-part variability in terms of materials and stack up geometry. These can significantly influence the cooling design, and it is important to be aware of their impact. In this study we focus on a stochastic analysis of a hypothetical multi core multi-threaded microprocessor. The power in each block is assumed to a random variable with fluctuations as high as +/-20% of the block nominal power. Additionally the thickness and conductivities of the die, TIM1, lid (heatspreader), TIM2 and the sink thermal performance are also considered as independent random variables. A detailed Monte Carlo analysis of the package coolability is conducted, considering one scenario where power fluctuation is enabled and the other where power is treated as being static. The findings highlight the significance of considering the realistic power fluctuations in the cooling solution design. Furthermore, the simulation data permit pareto analysis to identify the geometry/material characteristics that most significantly influence package coolability, so thermal designers can focus attention on those areas.
Abstract: In the high performance computing arena, the use of multi-core processors which support hardware threading is becoming more common. These advanced microprocessors are used in high end servers which perform intensive data manipulation, graphical visualization and floating point computations. To be able to support this demand for performance, each advancing generation of microprocessors features smaller transistor gate lengths than the preceding ones. As such, the semiconductor industry has moved from 130 nm process technology (circa 2000) to 65 nm technology (available today) and is moving towards the 45 and 32 nm technology (anticipated 2009 to 2010). As the transistor technology evolves and gate lithography shrinks, microprocessor power has continued to rise, and in particular the contribution of static leakage power to the total chip power continues to grow. Since the dynamic power (ie switching power) dissipated by a silicon chip is proportional to the square of the supply voltage and the frequency, a common theme to manage power in high end applications is through Dynamic Voltage and Frequency Scaling, or DVFS. In the course of normal die operation, the heat transferred from the chip to the ambient manifests in a temperature field in the cooling solution, and also in the hardware attached to the cooling solution- the package on which the chip is attached, the boards to which the chip package is attached, the electrical interconnect (socket) and so on. As is to be expected, with a DVFS policy in place the temperatures of the solder joints in the connector/socket are likely to be influenced; and the fluctuating temperatures are likely to cause aging of the solder joints, reduced connector life and ultimately the failure of the interconnect. As such, it is important to study the interaction of DVFS with overall connector reliability. To this end, in this study we focus on a sample application where a CPU module containing a thermal test vehicle is subjected to controlled laboratory thermal testing. The resulting temperature data are used in system identification studies to obtain linear, causal time-invariant models for the thermal behavior of the CPU junction, heatsink and connector temperatures as a function of dynamic power load. Chip temperature was sensed by a thermal diode, while all other temperatures were measured by thermocouples. Response to cyclic heat generation in the chip produced a frequency-dependent response at each temperature measurement location. The Bode plots for these models can be readily used to identify the frequency ranges of power fluctuation for which the chip, heatsink and connector temperatures are largely uninfluenced. Equivalently, the results of this study can also be used to identify power fluctuation frequencies which cause harmful temperature field fluctuations that in turn compromise solder joint reliability. Using this unified framework based on system identification provides the thermal engineer a valuable means to provide feedback to the chip design teams regarding the impact of power fluctuations, and helps recommend to the chip design teams 'thermally acceptable' ranges of power fluctuation frequencies to be used in conjunction with a DVFS policy.
Abstract: With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common therme in next-generation CPU offerings will be the use of dynamic voltage and frequency. Scaling (DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.
Abstract: A flip-chip package with square die is considered in this study. Up to four square non-intersecting hot blocks are imposed on the die's otherwise uniform power distribution. Block locations on the die outline are randomly chosen with uniform probability. The power density of a given block is a random parameter, and is permitted to be as high as 10times the baseline uniform bulk power density. Additionally, the size of any block is also treated as a random parameter and is permitted to be as high as 10 % of the die area. A 6000-tuple Monte Carlo study of the packages is conducted, and the package thermal resistance (Rjc) noted in each case. A variety of models are fit to the Rjc using the block characteristics as key variables, and their quality is characterized using the statistical correlation coefficient as a model metric. The results suggest a 96 % correlation between Rjc and the largest product of local power ratio and square of effective local power density ratio among the blocks- providing a simple and useful method to immediately identify blocks with the most impact on Rjc in a die floorplan.
Abstract: Traditional methods of TIM (thermal interface material) void content specification are often based on a worst case analysis and can often lead to conservative and expensive lid attach design/process development, especially in high performance microprocessor package designs that are the norm today. In a meaningful departure from such methods, we present a practical approach to specify the maximum void content using the methods of statistical analysis. Our approach lends itself to a simple design paradigm where the business side of the package development drives the concept of an acceptable fallout level (AFL) and the technical specifications dictate the acceptable coolable power loss (ACPL). Together, these concepts are tied to a unique void content specification that is significantly less conservative than a worst-case approach, and readily meets the requirements of the design. We illustrate this novel approach for the simple case of TIM voids that have an area-wise uniform probability distribution, and compare the findings with a traditional worst-case void content specification.
Abstract: Thermal Interface Materials (TIMs) are used as thermally
conducting media to carry away the heat dissipated by an
energy source (e.g. active circuitry on a silicon die). Thermal
properties of these interface materials, specified on vendor
datasheets, are obtained under conditions that rarely, if at all,
represent real life environment. As such, they do not accurately
portray the material thermal performance during a field
operation. Furthermore, a thermal engineer has no a priori
knowledge of how large, in addition to the bulk thermal
resistance, the interface contact resistances are, and, hence,
how much each influences the cooling strategy. In view of
these issues, there exists a need for these materials/interfaces to
be characterized experimentally through a series of controlled
tests before starting on a thermal design. In this study we
present one such characterization for a candidate thermal
interface material used in an electronic cooling application.
In a controlled test environment, package junction-to-case, Rjc,
resistance measurements were obtained for various bondline
thicknesses (BLTs) of an interface material over a range of die
sizes. These measurements were then curve-fitted to obtain
numerical models for the measured thermal resistance for a
given die size. Based on the BLT and the associated thermal
resistance, the bulk thermal conductivity of the TIM and the
interface contact resistance were determined, using the
approach described in the paper. The results of this study
permit sensitivity analyses of BLT and its effect on thermal
performance for future applications, and provide the ability to
extrapolate the results obtained for the given die size to a
different die size. The suggested methodology presents a
readily adaptable approach for the characterization of TIMs
and interface/contact resistances in the industry.
Abstract: When comparing two electronic packages identical in all
respects except die plan dimensions and power, wherein the
package with the smaller die is associated with a lower power,
it is often hypothesized that the lower-powered package would
have a lower junction-case thermal resistance. This hypothesis
is generally based on the questionable argument that because
the smaller package has lower power, its internal temperatures
should be lower and hence a lower junction-case resistance
should be 'intuitively' expected.
In this article we show that drawing inferences about
trends in junction-case resistance based merely on power
trends, as outlined above, can be incorrect. In order to address
this issue and provide better `indicators' for comparing thermal
performance across packages, we introduce the concept of the
Power Density Distribution (PDD) and show how it relates
with the junction-case thermal resistance. To illustrate its use
in comparing thermal performance of packages we consider
examples of several ICs with different die size/power
combinations.
Additionally, we also note the correlation between peaks
in the spatial distribution of the power density and those of the
die temperature distribution; in effect, this furnishes a simple
way to identify candidate hot-spot locations on the die without
resorting to extensive numerical thermal simulation/testing.
We illustrate this intuitively anticipated concept for a variety of
power distribution scenarios in some of our example IC
packages.
Abstract: In the industry, heatsinks have commonly been
oriented on IC packages so that their plan outlines are
edge-wise parallel to those of the package. However
there are situations where a rotated orientation is
preferable, wherein the plan outline of the package is not
`aligned' with that of the heatsink assembly- in other
words a situation where the heatsink location/orientation
remain unchanged while the package itself is rotated inplane.
Mechanical design considerations may drive the
need for such a non-traditional orientation, since the
rotated package is anticipated to have lower mechanical
stress levels in the silicon than the non-rotated one under
the same heatsink-induced clamping load.
In this study we examine the impact of such package
rotation(s) on both the junction temperature performance
of CPU packages and the package-level clamp-load
induced mechanical stresses. Results show that the
stress reduction in the rotated package is in the range of
15% to 60%. The thermal analysis also demonstrates
that the effects on the hot spot temperature with 45
degrees rotation is an increase of almost 2 oC compared
with the non-rotated die case. This increase in junction
temperature is expected to be even higher with lower
airflow as seen in typical computer systems. Thus it may
be inferred that it is important to consider the effects of
die rotation on package performances.
Abstract: For high-power electronic packages, it is
generally accepted that the package-sink interface
materials used in the thermal solution influence hot-spot
temperature(s) and junction-to-ambient thermal
resistance. In this article we show how these packageexterior
materials can noticeably influence across-die
temperature gradients also. The numerical results reveal
that the across-die thermal gradient can nearly double
over a narrow range of conductivities typical of
commercially available package-sink interface materials.
Results show that the chip hot-spot temperature can be
reduced 4 to 7 C by increasing the thermal interface
material conductivity from 1 to 3 W/mk. This
improvement can reduce the total thermal resistance
from chip to ambient.
Abstract: An uncertain nominally linear time varying system with structured plant perturbations that do not fully satisfy
the classical ‘matching conditions’ is considered. The exogenous disturbances acting on the system and the plant
nonlinearities are treated as uncertain, possibly time varying, and norm bounded (i.e. no statistical characterizations
are assumed). A controller design based on Lyapunov theory is presented which uses noise-free state feedback
measurements and renders the system dynamics both uniformly bounded and uniformly ultimately bounded within
a ‘tailorable’ neighborhood of the origin. An example application of a simple mechanical system with uncertain
inertia, stiffness, and damping characteristics subjected to uncertain external excitation is considered. Numerical
results for the control performance are presented demonstrating the effectiveness of the design. The proposed
formulation may be readily extended to the case of noisy state measurements.
Abstract: A procedure is presented for design of an active suspension for a Single Degree
Of Freedom (SDOF) quarter-car model with nonlinearities. Damping action in the
uncontrolled suspension is assumed to be provided by two viscous dampers (one with
simple linear behavior and the other with velocity-squared damping characteristics),
while its stiffness is modeled by a hysteretic spring. The active control uses noise-free
measurements of the (upward) displacement and velocity of the vehicle, and is based
on Lyapunov stability theory. It guarantees that all vehicle responses are uniformly
bounded and uniformly ultimately bounded within a certain neighbourhood of the zero
state. Physically, the control ensures that displacement and acceleration of the sprung
mass (i.e. the payload) are reduced, thereby increasing rider comfort level. To assess
the proposed design, a numerical example of a quarter-car model is considered, and
the ride quality of the actively controlled suspension is examined in presence of sys-
tem nonlinearities, vehicle acceleration/deceleration and road surface inhomogeneities.
Simulations quantifying the performance and effectiveness of the proposed control tech-
nique are presented and discussed.
Abstract: A Lyapunov method is presented for head position
control of a hard disk drive assembly with structured model
uncertainties in the presence of external unmodeled disturbances
and friction effects. The design involves magnitude bounds on the
external disturbance and the model parameter inaccuracies and
does not call for their statistical characterization. The control
is tested on a classical Voice Coil Motor (VCM) model, and is
seen to have promising performance for the assumed parameters.
Despite the disturbance, friction effects and model inaccuracies
it demonstrates robust head positioning capability with low track
access times and track misregistration levels.
Abstract: A deterministic Lyapunov control design is pre-
sented for the problem of head positioning in a disk drive
servomechanism subjected to external disturbance and friction
effects. The proposed technique only requires knowledge of an
upper bound on the magnitude of the time varying external
disturbance, and does not call for its detailed a priori temporal
or statistical characterization. The controller is demonstrated on
a commonly used Voice Coil Motor (VCM) model, and is noted
to have good head positioning performance for both track seek
and track follow modes in the presence of disturbance loads and
friction effects.
Abstract: A decoupling package stack including a circuit board, a substrate mounted on and electrically coupled to the circuit board, a semiconductor die mounted on and electrically coupled to the substrate a deformable elastomeric support mounted on the substrate, one or more mounts coupled to the circuit board and a heatsink. The heatsink includes a contoured heatsink base having a spacer attached thereto, the spacer operable to determine and maintain a desired bondline of a first thermal interface material (TIM) between the semiconductor die and the contoured heatsink base. The heatsink also includes one or more contact portions for contacting the deformable elastomeric support and one or more compressing surfaces coupled to the one or more mounts. A method for assembling a decoupling package stack.
Abstract: A heatsink includes a heatsink base, an elastomeric base, multiple slider pins and an alignment frame coupled to the heatsink base. The elastomeric base includes multiple holes, the elastomeric base coupled to the perimeter of the heatsink base. Each of the slider pins secured in one of the holes in the elastomeric base. The alignment frame supporting and aligning the slider pins as the slider pins move in a direction substantially perpendicular to the heatsink base. A method of assembling a heat spreader is also described.
