Abstract: The continuing drive toward high-density, low-profile Integrated Circuit packaging has accelerated the spread of flip-chip technology to laminated substrates, creating direct chip attach (DCA) configurations. However, the substantial difference in the coefficients of thermal expansion (CTE) between the chip and the laminated substrates makes DCA configurations vulnerable to thermally-induced strains and the resulting solder joint fatigue. The reliability of flip-chip technology is dramatically improved by âunderfillingâ the gap between the chip and substrate with epoxy. The present effort is aimed at exploring the benefits of underfilling in DCA configurations. The thermo structural behavior of an underfilled DCA is evaluated using FEM and employing an axisymmetric model of a typical DCA structure. Numerical simulations are performed for different sets of underfill material properties. The results are used to determine the parametric sensitivity of the thermal strain in the solder joints and the axial and shear stresses in the underfill material and to define the desirable range of underfill material properties. These results together with the Coffin-Manson relation are used to predict the theoretical improvement in cycles to failure. The results suggest that to minimize fatigue failure, the CTE of an underfill material should match that of solder material and its Young's Modulus should be as high as the adhesion strength of the underfill allows.
Abstract: Due to the high I/O density, low-cost assembly, and low package profile, DCA is the technology of choice in many current applications. However, DCA configurations are vulnerable to thermally induced strains and the resulting solder-joint fatigue, which, in turn, leads to reduced reliability. In recent years it has been found possible to obtain dramatically higher (5-10X) reliability and to operate successfully with much larger chip sizes, under comparable operating conditions and with identical solders, by underfilling a chip. Underfilling is done by filling the gap between the chip and substrate with epoxy, which also surrounds the solder joints. Underfilling between the chip and substrate reduces solder-joint deformation and shear strain.
Abstract: The fatigue life of an underfilled flip-chip package has been evaluated using the Coffin-Manson relation and finite element modeling (FEM)-computed solder shear strain for typical flip-chip structures. In the course of this effort, numerical simulations were performed for underfill materials of varying thermo-structural properties, two chip sizes, and two solder bump heights. The results were used to examine the parametric sensitivity of the thermal strain in the solder joints and the axial, as well as shear stress in the underfill material. The predicted improvement in the number of cycles-to-failure of the underfilled flip-chip was found to agree with empirical observation. However, the maximum improvement achievable by underfilling was found to be limited by the adhesion strength of the underfill material.
Abstract: This paper described a ceramic ball grid array (CBGA) and its second level reliability. The CBGA uses a substrate with high coefficient of thermal expansion (CTE) and leadfree soldering. The reworkability of the BGA package and board was also studied. The results have shown that this package is reworkable without a significant reliability reduction in the board level reliability. The reliability of solder joints in different chains is monitored and reported separately during the thermal cycling test to understand the impact of the distance to the neutral point. A finite element model of the test setup was created and modeling results were compared with the thermal cycling reliability test data. Acceleration factor has calculated for irregular temperature profiles as compared to the standard ATC profile. The impact of the highest temperature during the temperature cycle as well as the temperature range was shown to follow traditional Norris-Landzberg's equation. A recommendation is made to use the acceleration factor for translating the test data between different temperature cycling scenarios.
Abstract: We have evaluated a new Ag-filled silicone thermal
interface material (TIM) for its sensitivity to lid finish and
impact on imaging discontinuities in the die/lid (TIM1) layer,
in conjunction with two high performance lid materials, as a
part of our advanced packaging technology development
effort. Thermal and mechanical (shear stress and lid pull)
measurements have been carried out on a number of different
lid finishes to optimize thermal performance and adhesion at
the TIM1/lid interface. This silicone TIM1 is found to be
sensitive to the type of Ni-plating and plating bath chemistry.
Nondestructive and destructive metrology has been carried
out on flip chip (FC) packages using Ag-filled silicone TIM1
and either Cu or AlSiC lids. A number of silicone
formulations have been investigated to assess their impact on
surface acoustic microscopy (SAM) and X-ray imaging.
Nondestructive evaluation (NDE) by real time X-ray and
SAM has identified artifacts that make it difficult to
unambiguously detect voids and delamination in the TIM1
layer. A âdark ringâ or âpicture frameâ artifact is observed at
the die perimeter in acoustic microscope images of packages
with the Ag-filled TIM1. Detailed SEM cross-section and
thermal mapping analyses on a number of specially
constructed FC packages have been correlated with TIM1/lid
delamination and voiding observed in SAM and X-ray
images. Results of these studies point to changes in the TIM1
modulus during cure and post cure thermal excursions as the
cause of the âdark ringâ observed in the transmission SAM
images rather than delamination at the TIM1/lid or TIM1/die
interfaces. However, in the event that delamination is present
at the edges it cannot be unambiguously deconvoluted from
the âdark ringâ artifact in the SAM images.
Abstract: A test apparatus and methodology have been developed to provide accurate measurement of the thermal resistance of interface materials for predictive modeling simulations and selection of optimal cooling solution for high-power electronic modules. A guarded heat flow apparatus, based on the ASTM D5470 standard, using calibrated RTDs embedded in precision-machined meter blocks, has been developed to measure the bulk and contact thermal resistance of both single layers and stacked assemblies of thermal materials. This test station has demonstrated a differential temperature accuracy of 0.006 degC and a repeatability of <0.001 degC/W for a single layer of thermal interface material (TIM) for both 2-in. diameter and 1-in. square area test surfaces. A new test strategy has been developed to facilitate measurement of strongly adhesive TIMs in a bonded assembly. A thermal test vehicle composed of two non-instrumented heat spreader (HS) coupons directly bonded by an adhesive TIM is mounted between the GHF test surfaces. For a calibrated instrument TIM and well-controlled test vehicle geometry, the TIM joint resistance in OHFC Cu assemblies has been measured to an uncertainty of ~0.005 degC/W. We have verified that it is possible to extract both bulk and contact resistances within experimental accuracy. The method has been tested on a matrix of high performance TIMs and HS materials, including Cu and diamond composites, filled adhesives and metal (solder) interfaces. In addition, this technique has been used to compare the thermal performance of nominally "good" samples with those having defects, such as voids or delamination, in the thermal interface layer, and also to modeling predictions.
Abstract: Novel packaging materials with the promise of high thermal conductivity (TC) and low or tailored coefficients of thermal expansion (CTE) are increasingly available as heat spreaders and thermal interface materials (TIMs). We have evaluated a number of these materials including 2 diamond composites, Cu-ceramic functionally graded materials, baseline metal filled epoxies and 2 metallic or solder-based TIMS as part of our advanced technology development effort. Some of these materials are evolutionary while others represent disruptive changes to assembly of the standard package stack-up We will report on measurements made on thermal test structures in a guarded heat flow (GHF) system. Thermal performance measurements on test structures comprised of novel high performance materials will be compared with test structures made from well-characterized OFHC copper as well as lower TC materials such as CuW and silicon. Methodology employed to make accurate measurements of temperature differences across the test structures (best case differential is 0.006 °C, single point is 0.004 °C) will be described. In addition, GHF measurements may be compared with those made in a thermal flash system. Use of these materials can introduce voids and delamination to the thermal stack-up. Evaluation of microstructure and joining issues by CSAM, X-ray and SEM, focusing on voids and delamination introduced during assembly or thermal cycling of the test structures will also be presented.
Abstract: The paper parametrically assesses the impact of the voids/delamination on the system thermal performance. Analysis is carried out numerically and validated against experimental data (thermal measurements and C-SAM images). Topics covered include the relationship between voids/delamination and TIMsâ and heat spreaderâs effective thermal conductivity; sensitivity of the system thermal performance to void/delamination size and location; voids/delamination impact vs. chip power dissipation (uniform vs. non-uniform); comparison of TIM1 vs. TIM2 voids impact; and, finally, comparison of voids vs. delamination.
Abstract: Advances in processor design have been made possible in part by increases in the packaging density of electronics. At the same time, combination of increased power dissipation and packaging density has led to substantial growth in the chip and system heat fluxes and amplified complexity in electrical signal integrity and mechanical stack-up design in the recent years, particularly, in the high-end computers. With the trend towards miniaturization, heat removal, along with increased reliability requirements, has become a major bottleneck in product development, especially, in low profile systems, telecom servers and blades. Cooling of high heat flux components may require consideration of innovative open-loop, as well as plausible closed-loop, cooling designs for data centers.
This paper addresses reliability aspects of thermal, electrical, mechanical, and interconnect design and long-life operation of high-end air-cooling, as well as feasible active open and closed-loop cooling technologies of high heat flux processors.
Abstract: High performance thermal greases have been evaluated in three separate environments: ideal laboratory, in situ laboratory, and system mockup testing to better understand how bulk and interfacial thermal properties, in combination with the test vehicles used, effect the resultant thermal performance. The three methodologies are described and measurements on a baseline material reported.
Abstract: Paper defines test requirement guidelines for determining reliability and functionality of TIM2 materials to be used in Sun products. Test requirements are defined as guidelines, rather than strict specifications, due to the unique nature presented by various TIM materials and actual products. These guidelines are used by engineers engaged in cooling solution development, and are also beneficial to third party TIM suppliers interested in developing TIMs which pass Sun's standard. Since there is currently no industry-wide standards specifically for TIM2 qualification, Sun is interested in driving the adoption of all or part of these guidelines as the industry standard.
Abstract: Thermal design in electronic packaging is driven by the maximum allowable junction temperature of a CPU. An inadequate thermal design that underestimates the junction temperature may adversely impact the electrical performance of the CPU, making predicting the junction temperature a crucial step in package and system thermal design. A numerical model of a heat sink and thermal test package with a uniform and non-uniform power dissipation was created and used to predict their temperatures. The uniform power dissipation case was used to calibrate the numerical model's TIM2 thermal impedance. In the non-uniform power cases, the maximum heat flux was over four times higher than the average heat flux. The numerical analysis results in the non-uniform power cases yielded junction temperatures within 2 degrees of the measured values. The heat sink used in the tests as well as numerically modeled contained a vapor chamber base and a plate heat sink. Three different heat sink modeling approaches were used, including: detailed modeling of the heat sink, effective convection coefficient heff, and effective thermal conductivity keff. Test data was used to establish the effective heat transfer coefficient and effective thermal conductivity. A simplified heat sink numerical model allows the computational grid density to be significantly reduced, resulting in fast convergence. Alternate heat sink designs were also considered.
Abstract: Many advances in Complementary Metal Oxide Semiconductor (CMOS) technology (deep sub micron feature scales, GHz frequencies, and Silicon On Insulator (SOI)fabrication) have been made possible by increases in the packaging density of electronics. These advances began with the introduction of very large scale integration (VLSI). The combination of increased power dissipation and packaging density led to substantial growth in the chip and system heat fluxes, as well as the amplified complexity in electrical signal integrity and mechanical stackup design in the recent years, particularly in high-end computers. With the trend towards miniaturization, heat removal has become a major bottleneck in product development, especially, in low profile systems, telecom servers and blades. According to ITRS roadmap, power dissipation of high performance single chip packages is predicted to be in 218-288 W range, posing a serious challenge with no proven air-cooled solutions to exist.
Abstract: Thermal Interface Materials (TIMs) are used as thermally
conducting media to carry away the heat dissipated by an
energy source (e.g. active circuitry on a silicon die). Thermal
properties of these interface materials, specified on vendor
datasheets, are obtained under conditions that rarely, if at all,
represent real life environment. As such, they do not accurately
portray the material thermal performance during a field
operation. Furthermore, a thermal engineer has no a priori
knowledge of how large, in addition to the bulk thermal
resistance, the interface contact resistances are, and, hence,
how much each influences the cooling strategy. In view of
these issues, there exists a need for these materials/interfaces to
be characterized experimentally through a series of controlled
tests before starting on a thermal design. In this study we
present one such characterization for a candidate thermal
interface material used in an electronic cooling application.
In a controlled test environment, package junction-to-case, Rjc,
resistance measurements were obtained for various bondline
thicknesses (BLTs) of an interface material over a range of die
sizes. These measurements were then curve-fitted to obtain
numerical models for the measured thermal resistance for a
given die size. Based on the BLT and the associated thermal
resistance, the bulk thermal conductivity of the TIM and the
interface contact resistance were determined, using the
approach described in the paper. The results of this study
permit sensitivity analyses of BLT and its effect on thermal
performance for future applications, and provide the ability to
extrapolate the results obtained for the given die size to a
different die size. The suggested methodology presents a
readily adaptable approach for the characterization of TIMs
and interface/contact resistances in the industry.
Abstract: Inâplane temperature variations across a die, caused by
the differences in power densities, have an adverse effect on
the IC performance and reliability and could lead to functional
failures. Elimination or, at least, reduction of inâplane
temperature variations across the die, along with a decrease in
junction temperature, is one of the most important tasks of
thermal management in electronic packaging. Several
solutions addressing the problem are analyzed in the paper and
include possible changes in material properties of its
components and improvements in the overall cooling.
Thermal modeling results are presented in the paper, and
comparisons are made between the reviewed solutions. Use of
an interface material with engineered material properties was
found to be the best among the analyzed solutions.
Abstract: The continuing drive towards high-density, low-profile Integrated Circuit
packaging has accelerated the spread of flip-chip technology to laminated
substrates, creating Direct Chip Attach (DCA) configurations.
However, the substantial difference in the coefficients of thermal expansion
(CTE) between the chip and the laminated substrates makes DCA configurations
vulnerable to thermally-induced strains and the resulting solder joint fatigue.
The reliability of flip-chip technology is dramatically improved by
"underfilling" the gap between the chip and substrate with epoxy. The present
effort is aimed at exploring the benefits of underfilling in DCA configurations.
The thermo-structural behavior of an underfilled DCA is evaluated using FEM and
employing an axisymmetric model of a typical DCA structure. Numerical simulations
are performed for different sets of underfill material properties. The results are
used to determine the parametric sensitivity of the thermal strain in the solder
joints and the axial and shear stresses in the underfill material and to define
the desirable range of underfill material properties. These results together with
the Coffin-Manson relation are used to predict the theoretical improvement in
cycles to failure.
The results suggest that to minimize fatigue failure, the CTE of an underfill
material should match that of solder material and its Young's Modulus should be
as high as the adhesion strength of the underfill allows.
Abstract: Delamination and/or rupture of the die-attach layer are among the primary failure mechanisms in plastic IC packages and often lower the threshold for other mechanical, as well as electrical, failure mechanisms. Die-attach failure is generally caused by the thermal expansion (contraction) mismatch of dissimilar materials and the consequent development of axial and shear stresses in the adhesive and along the material interfaces. To enhance the reliability of plastic packaging it is thus desirable to select the most reliable and cost-effective die-attach material. Analysis of an ideal tri-material structure, using a force and momentum balance, makes it possible to derive analytical relations for the axial and shear stresses in a die-attach layer. Based on these analytical relations, which are validated against FEM results, the critical material properties can be selected and used for the development of Figures-of-Merit (FOM) for material selection. These FOMs are then used to evaluate the effects of moisture on the selection of the die-attach materials.
Abstract: The continuing drive towards high-density, low-profile integrated circuit packaging has accelerated the spread of flip-chip technology. The use of an area array of solder bumps for the electrical and mechanical, as well as thermal attachment of the chip to the substrate provides flip-chip technology with considerable advantages in cost, density, and electrical performance, relative to the use of conventional single-chip packages. Unfortunately, however the difference in the coefficients of thermal expansion, between the silicon die and the substrate, leads to substantial, thermally-induced strains, which can result in fatigue failure of the solder joints. This problem is exacerbated by the use of the larger chips now becoming available. In recent years it has been found possible to obtain dramatically-higher reliability and to operate successfully with much larger chip sizes by âunderfillingâ the gap between the chip and substrate with epoxy. The present effort is aimed at exploring the thermo-structural behavior of such underfilled chips and more firmly establishing the physical basis for the improved reliability of this packaging technology. The thermo-structural behavior of an underfilled flip-chip package has been evaluated using the structural FEM code NIKEDP and employing an axisymmetric model of a typical flip-chip structure. In the course of this effort, numerical simulations were performed for underfill materials of varying thermo-structural properties and two solder bump heights. The results were used to examine the parametric sensitivity of the thermal strain in the solder joints and the axial, as well as shear, stress in the underfill material. The Coffin-Manson relation is used to relate the increased number of cycles-to-failure to the solder strain reduction associated with the use of underfilling
Abstract: Temperature variations on a die, caused by the differences in power densities, have an adverse effect on the package performance and reliability. Elimination or, at least, reduction of temperature variations on the die becomes one of the most important tasks of thermal design. Three possible solutions aimed at reducing temperature variations are evaluated. Thermal modeling of these solutions is presented, along with their advantages and disadvantages. Comparisons are made between the solutions.
Abstract: A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device, applying non-adhesive film to the one or more components, identifying a primary component of the one or more components, and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device, removing the non-adhesive film from the heat rejecting device, placing a heatsink-attach thermal interface material on the one or more components, and placing the heat rejecting device on the corresponding one or more components.
Abstract: A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite interconnect. The die-attach composite interconnect includes a plurality of carbon nanotubes, solder bumps, and standoff balls disposed on the die to provide one or more connections to the substrate. A PCB-attached substrate package includes a substrate package and one or more die disposed on the substrate package. The substrate package is disposed on a PCB by a PCB-attach composite interconnect. The PCB-attach composite interconnect includes a plurality of carbon nanotubes, solder balls, and standoff balls disposed on the substrate package to provide one or more connections to the PCB.
Abstract: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.
Abstract: A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.
Abstract: A field-replaceable active pumped liquid heat sink module includes a liquid pump, a radiator, an optional receiver, and a gasketed cold heat exchanger box, all of which are connected together in a liquid pump loop through which a coolant such as water is circulated. The liquid pump, radiator, optional receiver and gasketed cold heat exchanger box are in a liquid pump loop and are self-contained in a field-replaceable active pumped liquid heat sink module. The heat sink module provides direct contact between the liquid coolant and the top portion of the targeted electronic component, which can be a CPU.
Abstract: A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wall is maintained in its conforming location by an adhesive.
Abstract: A device for the transfer of heat away from a heat source comprising a base having first and second surfaces a plurality of fins extending adjacent to the second surface of the base. The base further including a chamber disposed between the first surface and the second surface of the base. The chamber further including a divider disposed therein adjacent the first surface. A pump is also disposed within the chamber to circulate fluid within the chamber.
Abstract: Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.
Abstract: The present application describes a method and an apparatus for facilitating increased uniformity and diffusion of force transfer on a bare die electronic package for example, when such electronic package is attached to a circuit board. Additional force absorbent material is applied around a bare die in the bare die electronic package. The force applied to the bare die electronic package can be distributed to the additional force absorbent material. A curable force absorbent material is dispensed around the bare die in the bare die electronic package. The surface of the curable material is substantially parallel with the surface of bare die thus facilitating a substantially uniform force distribution through the bare die and curable material resulting in a robust bare die electronic package.
Abstract: In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. An alignment tool is used to align the spacer with the silicon die. A thermal conductor can be placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A die interface material is not necessarily applied between the silicon die and the thermal conductor. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. The spacer can facilitate force transfer from the thermal lid to the die. The spacer allows a thermal conductor to be affixed to the silicon die without use of a die interface. An alignment tool is used to align the spacer with the silicon die.
Abstract: In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. The thermal conductor is placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. The spacer facilitates force transfer from the thermal conductor to the die. In an embodiment, the thermal conductor can be removed and a second thermal conductor used to further facilitate heat transfer. In an enablement, a heat sink and heat sink interface are provided and further facilitate heat transfer from the package. The specification also teaches an integrated circuit package manufactured by the method taught. The specification also teaches a computer system including an integrated circuit package manufactured by the method taught.
Abstract: In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the perimeter portion of the heat spreader is selected from material with a lower CTE than the material for the center portion of the heat spreader.
