Yoann Tagro was born in Abidjan, Côte d’Ivoire, on December 21, 1981. He received respectively in 2006 and 2010 the MSEE degree in Microelectronics from the University of Lille, Lille, France and the Ph.D. degree in Electrical Engineering at the Institute of Electronic, Microelectronics and Nanotechnology (IEMN), Lille, France in partnership with STMicorelectronics. His main research interests are concerned mmW lab in-situ development, high-frequency noise characterization and modeling of CMOS, BiCMOS and HBT technologies. He is currently in Postdoctoral position at IEMN.
Abstract: The ability to realize flexible circuits integrating sensing, signal processing, and communicating capabilities is of central importance for the development of numerous nomadic applications requiring foldable, stretchable and large area electronics. A key challenge is however to combine high electrical performance (i.e. millimeter wave, low noise electronics) with mechanical flexibility required for chip form adaptivity in addition to highly stable electrical performance upon deformation. Here, we describe a solution based on ultimate thinning and transfer onto a plastic foil of high frequency (HF) CMOS devices initially processed on conventional silicon-on-insulator (SOI) wafers. We demonstrate a methodology relying on neutral plane engineering to provide high performance stability upon bending, by locating the active layer, i.e. the transistor channel, at the neutral fiber of the flexible system. Following this strategy, record frequency performance of flexible n-MOSFETs featuring fT/fMAX of 120/145 GHz, are reported with relative variations limited to less than 5% even under aggressive bending on cylinders with curvature radii down to 12.5 mm.
Abstract: In this work, the possibility of achieving GaN-on-Si devices for millimeter wave applications operating at high bias is demonstrated. It is shown that highly scaled AlN/GaN-on-Si double heterostructure enables us to significantly improve electron confinement under high electric field as compared to single heterostructure while delivering high carrier density (.2 Ã 1013 cm22). Subsequently, trapping effects can be minimized resulting in the highest GaN-on-Si output power density up to 40 GHz and at a drain bias of 15 V together with a record fmax close to 200 GHz. At higher bias, infrared camera analysis clearly shows that these devices are mainly limited by self-heating effects. Furthermore, low noise figure has been assessed on this heterostructure, promising integration of cost effective low noise and high power millimeter wave amplifiers.
Notes: Received 26 October 2012; Revised 7 March 2013
Abstract: We report on the millimeter-wave noise performance of AlN/GaN/AlGaN double heterostructure (DHFET) grown on a 100-mm Si substrate with low-noise properties up to 40 GHz. The ultrathin-barrier GaN DHFETs simultaneously exhibit high current density, high transconductance, and high frequency performance (above 100 GHz) while showing low dc-to-RF dispersion and low gate and drain leakage currents. Consequently, sub-1-dB minimum noise figure at 36 GHz with an associated gain of 7.5 dB has been achieved. To our knowledge, this is the best noise performance reported in the $hbox{K}_{rm a}$-band for any GaN device.
Abstract: GaN devices are of increasing interest because of their wide band gap and large polarization charge enabling high carrier densities and high breakdown voltage. In particular, GaN-on-Si transistors would allow benefiting from high performance well beyond GaAs and Si-based technologies at a competitive cost, while being fully compatible with mature CMOS technologies. Moreover, this would allow Europe to be fully independent from the US in term of SiC substrates. Recent improvement of GaN-on-Si growth quality has allowed impressive high power and low noise performances up to 26 GHz. However, several limitations like RF losses, trapping effects and poor breakdown voltage in highly scaled devices still prevent high-performance GaN-on-Si device operation in the Ka band and beyond. Recently, we proposed an ultrathin barrier AlN/GaN/AlGaN double heterostructure (DHFET) grown on highly resistive Si substrate in order to overcome these limitations. The use of this double heterostructure allows a unique combination of high current density, high breakdown voltage, low leakage current and high RF performance.
In this paper, high performance AlN/GaN/AlGaN-on-Si substrate with low noise figure and high power density at 40 GHz will be shown for the first time. Indeed, the possibility to achieve sub-100-nm-gate-length GaN-on-Si devices with low RF dispersion under high bias is demonstrated, enabling to set a first benchmark at 40 GHz with 2.5 W/mm at VDS = 15 V, mainly limited by RF losses and thermal issues. Furthermore, sub-1-dB minimum noise figure at 36 GHz with an associated gain of 7.5 dB have been achieved owing to the outstanding properties of the ultrathin barrier GaN-on-Si DHFETs. To our knowledge, this is the best noise performance reported in the Ka band for any GaN devices.
Abstract: In order to pursue Mooreâs law, the recent introduction of new Gate stack using High-k dielectrics and Metal Gate (H-k/MG) for CMOS has been a key point to downscale the âEquivalent Oxide Thicknessâ (EOT). Within this context, this paper intends to investigate RF and broadband noise performances of a recent Low Power (LP) 28-nm H-k/MG CMOS Bulk Technology. For this purpose, following a selection of the best transistor featuring the best trade-off for fT/fMAX, S-parameters have been measured up to 110GHz to accurately determine multi-bias point RF Small Signal Equivalent Circuit (SSEC), required to extract a two-temperature noise model. The technology offers a minimum noise figure NFmin of 0.8dB (with an associated gain Ga equal to 14dB) @20GHz, for a DC drain current of 135mA/mm. The extracted two-temperature noise model has been verified both in W band and through tuner based noise measurement in [6-18 GHz] frequency range. Finally, the noise performance have been benchmarked with the best ones reported for H-k/MG CMOS technology up-to-date.
Abstract: This letter provides an experimental demonstration of high-performance industrial MOSFETs thinned down to 5.7 μm and transferred onto a 125-μm-thick polyethylene naphthalate foil. The die stack transferred onto the organic substrate comprises the 200-nm-thick active layer and the 5.5-μm-thick interconnection multilayer stack resulting in a light, compact, and bendable thin film. We unveil that dc and RF performances are invariant even for ultimate thinning down to the buried oxide layer. Furthermore, n-MOSFET performance is improved by 1.5à compared with previous work, and the first demonstration of 100-GHz p-MOSFETs on an organic substrate is presented. Unity-current-gain cutoff and maximum oscillation frequencies as high as 150/160 GHz for n-MOSFETs and 100/130 GHz for p-MOSFETs on a plastic substrate have been measured, respectively.
Abstract: This letter presents high frequency noise measurements carried out for MOSFETs in W-band (75-110 GHz). Because the 50 ?? noise figure of 65 nm node MOSFETs is higher than 10 dB in W-band, pre-matched structures covering the entire band have been developed to reduce the noise figure and to increase the gain. Then, in order to validate the 2 temperatures noise model in W-band, only F50 measurements of pre-matched structures are necessary.
Abstract: In order to pursue Moore's law, the recent introduction of new Gate stack using High-k dielectrics and Metal Gate (H-k/MG) for CMOS has been a key point to downscale the âequivalent oxide thicknessâ (EOT). Within this context, this paper intends to investigate RF noise performance of a recent Low Power (LP) 28-nm H-k/MG CMOS Technology. For this purpose, S-parameters have been measured up to 110GHz to accurately extract an RF Small Signal Equivalent Circuit (SSEC), required to extract a two-temperature noise model. The technology offers a minimum noise figure NFmin of 0.8dB (with an associated gain Ga equal to 14dB) @20GHz, for a DC drain current of 135mA/mm: these performances well compete with those previously reported for other H-k/MG technology.
Abstract: In this work, we report on the RF performance and noise characteristics of 65nm SOI-CMOS technology transferred onto plastic films. After transfer bonding onto a thin flexible substrate, RF-SOI-MOSFETs are shown to feature high unity-current-gain cut-off and maximum oscillation frequencies fT/fMAX amounting to 150/160GHz for n-type and 110/130GHz for p-type, respectively. Minimal noise figure and associated gain NFmin/Ga of 0.57dB/17.8dB and 0.57dB/17.0dB are measured at 10GHz for n- and p-MOSFETs, respectively.
Abstract: In this paper, high frequency (HF) noise performance of 65nm SOI n-MOSFETs, initially fabricated on rigid substrate and subsequently reported on flexible substrate (plastic), is presented for the first time. AC and noise performance is extracted from S-parameters measurements performed up to 110 GHz and noise measurements in 6-40 GHz frequency range, respectively. Almost no degradation has been observed between the S parameters measured on SOI rigid 65 nm transistors (referred as Rigid SOI-MOS) and the same thinned transistors transfer-bonded on a flexible substrate (referred to as Flex SOI-MOS). For Flex SOI-MOS, a minimum noise figure (NFmin) as low as 1.1 dB is achieved at 20 GHz, along with an associated gain (Ga) of 14.5 dB, when the transistor is biased at Vds=1.2V and Ids=270 mA/mm: so far, this performance constitutes the best reported one for flexible electronics.
Abstract: In this paper, for the first time, silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) millimeter wave (MMW) noise parameters (NFmin, Rn, Gammaopt) extraction through multi-impedance method. This tuner is directly integrated in on-wafer tested transistor test structure. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60 GHz up to 110 GHz for CMOS and BiCMOS sub 65 nm technologies characterization. |Gamma| of 0.88 have been achieved at the DUT input in the considered frequency range and tuner insertion losses are less than 20 dB.
Abstract: In this paper, for the first time, silicon integrated tuner is presented to extract SiGe:C transistor (HBT) millimeter wave (MMW) noise parameters (NFmin, Rn, Gammaopt) extraction through multi-impedance method. This Tuner is directly integrated On-Wafer at the transistor test structure level. Design and electrical simulation of the tuner are described demonstrating capability from 60 GHz up to 110 GHz for BiCMOS 130 nm technologies characterization. |GammaSMAX| up to 0.75 has been achieved at the DUT input in this frequency range and NFmin of 2.6 dB has been extracted on tested device @ 77 GHz.
Abstract: In this paper, the design and use of an in-situ tuner (IST) aiming on-wafer multi-impedance method are presented. The conventional method using off-wafer tuner is limited by the frequency range and has losses between this external Tuner and the device under test (DUT). Here, IST is placed near the DUT to achieve higher |Gamma| and to cancel losses between the impedance generator and the device. The architecture of the Tuner is based on variable lumped R and C elements fulfilled with Cold-FET and varactors controlled through biasing and associated to coplanar transmission line (cpw-TL) for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the 4 noise (NFmin, Rn, Gammaopt) parameters of a 65 nm MOSFETs silicon transistor through the use of this in-situ multi-impedance method. The 75-110 GHz noise test bench using cold-noise source method and the noise measurement are described showing Transistor capabilities at MMW.
Abstract: In this paper, for the first time, Silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) millimeter wave (MMW) noise parameters (NFmin, Rn, Gammaopt) extraction through multi-impedance method. This Tuner is directly integrated in On-wafer tested transistor test structure. The achieved proximity between device under test (DUT) and the developed Tuner allows better impedances (higher |Gammaopt|) for frequency above 60 GHz due to losses reduction between tuner and transistor compared to classical setup using off-wafer impedance generator. The tuner design is based on variable R, C elements fulfilled with cold-FET and varactors controlled through biasing and associated to transmission lines (TL) for phase shifting. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60 GHz up to 110 GHz for CMOS and BiCMOS sub 65 nm technologies characterization. |Gamma| of 0.88 have been achieved at the DUT input in the considered frequency range and Tuner losses are less than 20 dB.
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